Ruige Lee
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cb2c4f46e5
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拉出测试IO
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2025-08-12 17:48:35 +08:00 |
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Ruige Lee
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107895f6e0
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Revert "4多相位效果明显更好"
This reverts commit 7338314c17.
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2025-08-12 09:55:43 +08:00 |
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Ruige Lee
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7338314c17
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4多相位效果明显更好
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2025-08-11 19:33:56 +08:00 |
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Ruige Lee
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b0b221e8b0
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16相位操作还是卡
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2025-08-11 18:13:58 +08:00 |
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RuigeLee
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424e07a076
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增加5选3多数表决滤波
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2025-08-09 22:22:19 +08:00 |
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Ruige Lee
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8c09a6c4aa
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写死16相位
Merge branch 'mp_eb_dev' into feature/multiPhaseCDRIn
# Conflicts:
# src/main/scala/backBoard/ebus/CDRIn.scala
# src/main/scala/backBoard/shin/ShinTop.scala
# tb/shinTest/ShinTopSpiTb.v
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2025-08-05 16:49:41 +08:00 |
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656986a8ab
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:Merge branch 'feature_shintop' into eb_dev
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2025-07-30 23:14:37 +08:00 |
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Ruige Lee
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8ba8ff0e9e
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**抹除**加密特性
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2025-07-30 15:36:18 +08:00 |
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Ruige Lee
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302893c3e7
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加入CDR的滤波，并修改测试led
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2025-07-28 14:31:45 +08:00 |
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Ruige Lee
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9f88d26ba1
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多相位时钟可以使用
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2025-07-22 11:49:33 +08:00 |
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Ruige Lee
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7c632c8c1b
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编译通过
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2025-07-22 09:35:06 +08:00 |
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Ruige Lee
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bf8fce2671
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需要考虑多项位时钟是按同步时钟还是异步时钟处理
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2025-07-17 17:47:59 +08:00 |
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Ruige Lee
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1319027c9e
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代码清理
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2025-07-17 17:22:08 +08:00 |
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Ruige Lee
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a4515146f7
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加密特性长度修复
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2025-05-22 17:28:31 +08:00 |
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Ruige Lee
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944255978a
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增加加密特性（未测试）
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2025-05-22 16:53:42 +08:00 |
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Ruige Lee
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fb8bc91947
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暂时改回4倍采样以实现FPGA逻辑
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2025-05-13 17:05:38 +08:00 |
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Ruige Lee
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b55deb239f
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尝试速率配平，回环改到phy上
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2025-05-07 18:12:01 +08:00 |
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Ruige Lee
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19f4140dec
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尝试加入cdr模块，主站上行rsp， tlast还有亚稳态
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2025-05-06 17:39:52 +08:00 |
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Ruige Lee
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6c6cce1222
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CDRIn采样率改为8x，允许参数化
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2025-04-02 15:44:32 +08:00 |
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Ruige Lee
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1c7eb4ce47
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使用未使用4b/5b编码作为preamble
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2025-03-04 10:58:59 +08:00 |
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Ruige Lee
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ecff635e83
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删除CDR中的硬件CDR
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2025-02-11 15:17:02 +08:00 |
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Ruige Lee (WSL)
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33f2160365
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修复错误位宽，加入islast
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2025-01-17 16:21:46 +08:00 |
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Ruige Lee (WSL)
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134440812b
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compile without tl2cdr
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2025-01-09 19:10:07 +08:00 |
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RuigeLee
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404c973671
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使用4b/5b加跳变时钟选择法升级CDR
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2025-01-09 17:21:10 +08:00 |
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RuigeLee
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394854cdce
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回去调spi模块，临时提交，后续需要审查
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2024-12-02 15:00:03 +08:00 |
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RuigeLee
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2750a8e2f7
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规范跨时钟保护，有效果
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2024-11-12 17:52:36 +08:00 |
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RuigeLee
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392ebf902c
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优先级mux引入了额外的一拍数据
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2024-11-12 15:55:20 +08:00 |
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RuigeLee
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5d6151b2ac
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清理代码
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2024-11-05 11:13:36 +08:00 |
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RuigeLee
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9fa54072f4
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bug payload 12bits
总线握手条件
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2024-11-04 14:39:26 +08:00 |
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RuigeLee
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983f9e771d
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debug开始，cdrin优化后payloadlen加载错误
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2024-11-01 18:09:16 +08:00 |
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RuigeLee
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46882b6b4d
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缩减后面积已经满足要求，时序违例，主要集中在alu和访存接口
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2024-10-31 17:38:12 +08:00 |
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RuigeLee
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7e99cf4489
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1SRAM加入仿真随机初始化；2CDR物理层重新对齐包头 3复制粘贴变量错误
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2024-10-17 15:32:16 +08:00 |
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RuigeLee
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d449980b5b
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物理层和链路层的包头一起合并处理
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2024-10-17 11:54:02 +08:00 |
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RuigeLee
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a6068fbda0
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新主站发送逻辑
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2024-10-09 17:37:15 +08:00 |
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RuigeLee
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753586a65e
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正确锁住，丢包率大
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2024-09-23 17:52:59 +08:00 |
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RuigeLee
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10b2e4c78f
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Revert "最后几个比特锁不住"
This reverts commit 97211f0962.
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2024-09-23 17:40:35 +08:00 |
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RuigeLee
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97211f0962
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最后几个比特锁不住
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2024-09-23 17:40:23 +08:00 |
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RuigeLee
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833ad07525
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采样头对齐问题，对齐哪个55和D5
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2024-09-23 17:23:34 +08:00 |
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RuigeLee
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6750593b48
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发送改用标志头锁时钟通道方案
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2024-09-23 16:44:44 +08:00 |
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RuigeLee
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3c357b54e0
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4倍频采3次
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2024-09-20 14:55:43 +08:00 |
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RuigeLee
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1368e9037d
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CDR基本测试通过
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2024-09-19 15:23:38 +08:00 |
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RuigeLee
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57c81d5cac
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CDRin编译通过
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2024-09-12 17:48:50 +08:00 |
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