Ruige Lee
|
573a1ad45f
|
bug:滤波需要顺序打拍，防止边界上跳变
|
2025-08-14 19:15:09 +08:00 |
|
RuigeLee
|
424e07a076
|
增加5选3多数表决滤波
|
2025-08-09 22:22:19 +08:00 |
|
Ruige Lee
|
8c09a6c4aa
|
写死16相位
Merge branch 'mp_eb_dev' into feature/multiPhaseCDRIn
# Conflicts:
# src/main/scala/backBoard/ebus/CDRIn.scala
# src/main/scala/backBoard/shin/ShinTop.scala
# tb/shinTest/ShinTopSpiTb.v
|
2025-08-05 16:49:41 +08:00 |
|
|
|
656986a8ab
|
:Merge branch 'feature_shintop' into eb_dev
|
2025-07-30 23:14:37 +08:00 |
|
Ruige Lee
|
8ba8ff0e9e
|
**抹除**加密特性
|
2025-07-30 15:36:18 +08:00 |
|
Ruige Lee
|
302893c3e7
|
加入CDR的滤波，并修改测试led
|
2025-07-28 14:31:45 +08:00 |
|
Ruige Lee
|
9f88d26ba1
|
多相位时钟可以使用
|
2025-07-22 11:49:33 +08:00 |
|
Ruige Lee
|
7c632c8c1b
|
编译通过
|
2025-07-22 09:35:06 +08:00 |
|
Ruige Lee
|
bf8fce2671
|
需要考虑多项位时钟是按同步时钟还是异步时钟处理
|
2025-07-17 17:47:59 +08:00 |
|
Ruige Lee
|
1319027c9e
|
代码清理
|
2025-07-17 17:22:08 +08:00 |
|
Ruige Lee
|
a4515146f7
|
加密特性长度修复
|
2025-05-22 17:28:31 +08:00 |
|
Ruige Lee
|
944255978a
|
增加加密特性（未测试）
|
2025-05-22 16:53:42 +08:00 |
|
Ruige Lee
|
fb8bc91947
|
暂时改回4倍采样以实现FPGA逻辑
|
2025-05-13 17:05:38 +08:00 |
|
Ruige Lee
|
b55deb239f
|
尝试速率配平，回环改到phy上
|
2025-05-07 18:12:01 +08:00 |
|
Ruige Lee
|
19f4140dec
|
尝试加入cdr模块，主站上行rsp， tlast还有亚稳态
|
2025-05-06 17:39:52 +08:00 |
|
Ruige Lee
|
6c6cce1222
|
CDRIn采样率改为8x，允许参数化
|
2025-04-02 15:44:32 +08:00 |
|
Ruige Lee
|
1c7eb4ce47
|
使用未使用4b/5b编码作为preamble
|
2025-03-04 10:58:59 +08:00 |
|
Ruige Lee
|
ecff635e83
|
删除CDR中的硬件CDR
|
2025-02-11 15:17:02 +08:00 |
|
Ruige Lee (WSL)
|
33f2160365
|
修复错误位宽，加入islast
|
2025-01-17 16:21:46 +08:00 |
|
Ruige Lee (WSL)
|
134440812b
|
compile without tl2cdr
|
2025-01-09 19:10:07 +08:00 |
|
RuigeLee
|
404c973671
|
使用4b/5b加跳变时钟选择法升级CDR
|
2025-01-09 17:21:10 +08:00 |
|
RuigeLee
|
394854cdce
|
回去调spi模块，临时提交，后续需要审查
|
2024-12-02 15:00:03 +08:00 |
|
RuigeLee
|
2750a8e2f7
|
规范跨时钟保护，有效果
|
2024-11-12 17:52:36 +08:00 |
|
RuigeLee
|
392ebf902c
|
优先级mux引入了额外的一拍数据
|
2024-11-12 15:55:20 +08:00 |
|
RuigeLee
|
5d6151b2ac
|
清理代码
|
2024-11-05 11:13:36 +08:00 |
|
RuigeLee
|
9fa54072f4
|
bug payload 12bits
总线握手条件
|
2024-11-04 14:39:26 +08:00 |
|
RuigeLee
|
983f9e771d
|
debug开始，cdrin优化后payloadlen加载错误
|
2024-11-01 18:09:16 +08:00 |
|
RuigeLee
|
46882b6b4d
|
缩减后面积已经满足要求，时序违例，主要集中在alu和访存接口
|
2024-10-31 17:38:12 +08:00 |
|
RuigeLee
|
7e99cf4489
|
1SRAM加入仿真随机初始化；2CDR物理层重新对齐包头 3复制粘贴变量错误
|
2024-10-17 15:32:16 +08:00 |
|
RuigeLee
|
d449980b5b
|
物理层和链路层的包头一起合并处理
|
2024-10-17 11:54:02 +08:00 |
|
RuigeLee
|
a6068fbda0
|
新主站发送逻辑
|
2024-10-09 17:37:15 +08:00 |
|
RuigeLee
|
753586a65e
|
正确锁住，丢包率大
|
2024-09-23 17:52:59 +08:00 |
|
RuigeLee
|
10b2e4c78f
|
Revert "最后几个比特锁不住"
This reverts commit 97211f0962.
|
2024-09-23 17:40:35 +08:00 |
|
RuigeLee
|
97211f0962
|
最后几个比特锁不住
|
2024-09-23 17:40:23 +08:00 |
|
RuigeLee
|
833ad07525
|
采样头对齐问题，对齐哪个55和D5
|
2024-09-23 17:23:34 +08:00 |
|
RuigeLee
|
6750593b48
|
发送改用标志头锁时钟通道方案
|
2024-09-23 16:44:44 +08:00 |
|
RuigeLee
|
3c357b54e0
|
4倍频采3次
|
2024-09-20 14:55:43 +08:00 |
|
RuigeLee
|
1368e9037d
|
CDR基本测试通过
|
2024-09-19 15:23:38 +08:00 |
|
RuigeLee
|
57c81d5cac
|
CDRin编译通过
|
2024-09-12 17:48:50 +08:00 |
|
