Ruige
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ba04725e72
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Revert "尝试跨时钟域QSPI，失败"
This reverts commit 5ccf101648.
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2025-09-09 17:50:22 +08:00 |
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RuigeLee
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5ccf101648
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尝试跨时钟域QSPI，失败
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2025-09-09 17:48:52 +08:00 |
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Ruige
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42139b5bcc
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Merge branch 'mp_eb_dev' of github.com:whutddk/RISCV-MAC-SWICH into mp_eb_dev
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2025-09-09 16:11:57 +08:00 |
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RuigeLee
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22cc6ef0b8
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微调spi访存时间点，提高理论极限频率
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2025-09-09 16:10:19 +08:00 |
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58b65da129
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增加8b10b的测试用例，并与4b5b共享测试用例
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2025-09-09 01:21:02 +08:00 |
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b51b56688a
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调整异频异相时钟的测试参数
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2025-09-08 23:41:59 +08:00 |
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cc51f206de
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修正clk仿真的代码，可以通过测试
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2025-09-08 23:17:29 +08:00 |
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Ruige
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2b1f01274b
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Merge branch 'mp_eb_dev' of github.com:whutddk/RISCV-MAC-SWICH into mp_eb_dev
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2025-09-08 21:50:15 +08:00 |
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RuigeLee
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a6a546a0f9
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完成对4b5b，8b10b的覆盖测试
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2025-09-08 21:49:56 +08:00 |
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73b773e286
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对顶层文件中的错误修改,使得仿真可以正常运行
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2025-09-08 18:51:41 +08:00 |
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fa1327aa5f
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修改测试用例数据,回归通过
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2025-09-08 18:25:05 +08:00 |
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31b362b291
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增加8b10b打开关闭的开关
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2025-09-08 18:25:05 +08:00 |
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RuigeLee
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561f394b16
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sReg.isLVDSWriteAble 锁定lvds写入syncPoint和synccfg
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2025-09-08 17:48:08 +08:00 |
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Ruige
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43b70e674c
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Merge branch 'mp_eb_dev' of github.com:whutddk/RISCV-MAC-SWICH into mp_eb_dev
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2025-09-08 17:10:09 +08:00 |
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RuigeLee
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1d5a257b58
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Merge branch 'mp_eb_dev' into feature/syncSpi
# Conflicts:
# src/main/scala/backBoard/shin/SpiInterface.scala
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2025-09-08 17:07:10 +08:00 |
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RuigeLee
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c3c3a25e77
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修复spicmd没有在每次传输前后复位地问题，或许将导致三态门状态错误
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2025-09-08 17:02:43 +08:00 |
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9c43daf51e
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为多相位模拟增加命令行,增加8b10b切换的测试
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2025-09-08 16:47:30 +08:00 |
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a63e14e6f6
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增加代码,1.仿真了最多202个从站,功能正常;2.测试了读写\广播等操作
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2025-09-08 13:12:18 +08:00 |
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41d4805841
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备份代码，几个问题：1.打印消息超过63个设备后，设备号正确，但是从0开始；2.128个设备的话，末尾的2个设备不正确，不知道为什么
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2025-09-08 01:23:14 +08:00 |
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7d7f92e2fe
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增加测试用例的结果，修正部分测试用例
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2025-09-07 23:15:13 +08:00 |
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RuigeLee
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777ca7319b
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修复合并过程中位宽错误
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2025-09-07 22:35:32 +08:00 |
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a410c7ba67
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增加错误的比对,虽然不能完全意料结果,但是可以作为补充,节省精力
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2025-09-07 18:44:53 +08:00 |
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1958f196f5
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修改测试方案
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2025-09-07 07:37:34 +08:00 |
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3678b24318
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比较文件中增加单行x忽略比较
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2025-09-07 00:52:17 +08:00 |
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806b27474f
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按照最新得提交，已经仿真成功
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2025-09-07 00:42:46 +08:00 |
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dd6e2548a1
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增加ShinRelease发布命令行
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2025-09-07 00:31:28 +08:00 |
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8a7e4981fb
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将vcs仿真流程修正得更好
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2025-09-07 00:10:57 +08:00 |
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RuigeLee
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4a21e4b2ba
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修复接线错误
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2025-09-06 23:02:10 +08:00 |
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0b0a42afb0
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使用vcs编译通过,还有一些琐细的问题要解决
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2025-09-06 20:25:56 +08:00 |
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ed128f8ca3
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增加vcs下仿真文件，尚未调试通过，仅备份
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2025-09-06 20:03:45 +08:00 |
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0f33da4085
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更新测试数据
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2025-09-06 19:07:10 +08:00 |
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0b88e669a3
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增加异频异相时钟的相位参数
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2025-09-06 18:18:50 +08:00 |
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9b5848e1d7
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将波形输出改为fst格式
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2025-09-06 17:50:17 +08:00 |
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6e1232be94
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从版本库里把base.tc30捞回来
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2025-09-06 16:39:20 +08:00 |
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65322ba838
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保存合并后的测试解决方案,尚未完全验证
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2025-09-06 16:10:49 +08:00 |
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0c76190720
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整理测试用例
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2025-09-06 15:51:04 +08:00 |
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d9da8fe7db
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修正测试用例
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2025-09-06 15:20:35 +08:00 |
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e0c0bf1437
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修改测试寄存器的用例
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2025-09-06 15:20:35 +08:00 |
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RuigeLee
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ff7aba38ad
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拆分CDRIn为采样部分和axis部分；调整层次结构，仅将cdrInSample放在顶层；放置3组CDRInSample，使用寄存器选择
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2025-09-06 11:07:41 +08:00 |
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RuigeLee
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ac118289b2
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修复语法错误
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2025-09-05 19:30:35 +08:00 |
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RuigeLee
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4bc5e2927e
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修改key策略
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2025-09-05 17:15:04 +08:00 |
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RuigeLee
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d5523eaa46
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Merge branch 'feature/clk3_shift_allow' into mp_eb_dev
# Conflicts:
# src/main/scala/backBoard/ebus/CDRIn.scala
# tb/shinTest/ShinTopSpiTb.v
# tb/shinTest/gen_pkt.py
# tb/shinTest/testcase/base.py
# tb/shinTest/testcase/environment.py
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2025-09-05 16:01:52 +08:00 |
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RuigeLee
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7ec88aa3a7
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Merge branch 'feature/8b10b' into mp_eb_dev
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2025-09-05 15:43:02 +08:00 |
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RuigeLee
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7b3b4c010d
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8B10B正负相写反
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2025-09-05 15:39:17 +08:00 |
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RuigeLee
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e9bc1d1e18
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cdrin的preamble连续监控10个cycle
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2025-09-05 15:09:52 +08:00 |
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RuigeLee
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adb1d9c1c8
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4b5b 8b10b接线完成
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2025-09-05 12:55:32 +08:00 |
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5f510d53e1
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修正测试用例,贴和最新的SM提交和回退机制
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2025-09-05 11:22:56 +08:00 |
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RuigeLee
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26344d60cd
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写完编解码模块
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2025-09-05 11:11:01 +08:00 |
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RuigeLee
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b1825607ab
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修复中断丢脉冲问题，但每次脉冲宽度比设置多一拍
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2025-09-05 09:58:43 +08:00 |
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RuigeLee
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f609945a6a
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8b10b编码完成
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2025-09-05 09:35:29 +08:00 |
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