Ruige Lee
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f3a44f0b31
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slv
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2023-08-18 12:10:47 +00:00 |
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RuigeLee
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6fa2ef5f6e
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porta
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2023-08-16 22:25:30 +08:00 |
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Ruige Lee
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bbd0f0b887
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sync
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2023-08-16 06:12:49 +00:00 |
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Ruige Lee
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6c2f0b02f8
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FSMC
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2023-08-15 08:42:56 +00:00 |
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Ruige Lee
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939fa22be5
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wrapper of mst and slv
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2023-08-15 02:59:10 +00:00 |
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RuigeLee
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3211e21e11
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wrapper
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2023-08-14 22:46:50 +08:00 |
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RuigeLee
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1c7a226a70
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add function demo
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2023-08-09 14:43:24 +08:00 |
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RuigeLee
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68e0a6a055
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test pass
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2023-08-07 11:40:14 +08:00 |
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RuigeLee
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a041c7732a
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over sample in spi
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2023-08-07 10:15:56 +08:00 |
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RuigeLee
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d09aff40f2
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timing close
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2023-08-02 15:17:16 +08:00 |
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RuigeLee
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5d43600680
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fpga sync
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2023-08-01 15:50:53 +08:00 |
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RuigeLee
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35e6fcdb52
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mst test pass
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2023-08-01 14:44:05 +08:00 |
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RuigeLee
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24800cce9d
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spi compile pass
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2023-07-31 22:56:09 +08:00 |
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RuigeLee
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3aa4ca17d4
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all test pass
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2023-07-28 20:42:35 +08:00 |
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RuigeLee
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2048a4d286
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first test
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2023-07-28 15:38:46 +08:00 |
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Ruige
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85fe9175e6
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backplaneslv compile pass
Signed-off-by: Ruige <295054118@whut.edu.cn>
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2023-07-25 21:05:43 +08:00 |
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RuigeLee
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b1fd2db2e0
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backboard
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2023-07-24 19:31:32 +08:00 |
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