Ruige Lee
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23fdd91ba3
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修复：读取地址错位
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2025-05-16 15:39:17 +08:00 |
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Ruige Lee
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d5db3aebdb
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修正：单写单读从站写入访问时序问题
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2025-05-16 14:51:52 +08:00 |
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a32cd3c8c7
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add code comment.
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2025-05-15 18:40:26 +08:00 |
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Ruige Lee
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f20efe5b25
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实现同步sync信号的产生，编译未过
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2025-05-15 18:40:01 +08:00 |
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Ruige Lee
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f71b8553cb
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sync包的定点替换 0x25寄存器
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2025-05-15 14:57:58 +08:00 |
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Ruige Lee
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30df59220f
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Merge branch 'dev/qspi' into feature/ShinTop
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2025-05-14 16:27:25 +08:00 |
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Ruige Lee
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ed9bf22016
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QSPI修正可用
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2025-05-14 16:26:20 +08:00 |
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Ruige Lee
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2e186a8365
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搭建QSPI
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2025-05-13 18:03:22 +08:00 |
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Ruige Lee
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fb8bc91947
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暂时改回4倍采样以实现FPGA逻辑
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2025-05-13 17:05:38 +08:00 |
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Ruige Lee
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a39a15e1d0
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spi拉通
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2025-05-13 11:32:38 +08:00 |
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Ruige Lee
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51f941a8a6
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spi 成功触发主机发送
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2025-05-13 10:31:35 +08:00 |
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Ruige Lee
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20b94fbe44
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测试改逻辑电路实现，明天重新调
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2025-05-12 19:52:30 +08:00 |
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Ruige Lee
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afa1b9864f
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执行第一个task块
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2025-05-12 15:41:11 +08:00 |
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Ruige Lee
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e079103037
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spi已经加入，操作必要寄存器已加入，编译通过，未开始测试
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2025-05-09 17:44:54 +08:00 |
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Ruige Lee
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f05b61542c
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SM主从统一
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2025-05-09 16:11:18 +08:00 |
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Ruige Lee
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605f78c445
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首先搭建spi接口（未编译），采样时钟与主系统时钟同步，影响SPI sck最高频率，注意辅助拍的影响
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2025-05-08 17:43:10 +08:00 |
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Ruige Lee
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3810298986
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加入phy层测试完成
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2025-05-08 11:22:04 +08:00 |
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Ruige Lee
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b55deb239f
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尝试速率配平，回环改到phy上
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2025-05-07 18:12:01 +08:00 |
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Ruige Lee
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19f4140dec
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尝试加入cdr模块，主站上行rsp， tlast还有亚稳态
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2025-05-06 17:39:52 +08:00 |
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Ruige Lee
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9d53e4ea82
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同步测试完成
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2025-04-30 17:09:30 +08:00 |
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Ruige Lee
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031cffab24
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测试读写
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2025-04-30 15:15:09 +08:00 |
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Ruige Lee
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65c5aba8ce
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完成探针和索引
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2025-04-29 17:48:57 +08:00 |
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Ruige Lee
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b0ecbcc983
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从站默认自己最后一个设备，闭合上行回路
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2025-04-29 16:02:01 +08:00 |
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Ruige Lee
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a93c767240
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临时增加一个fifo以适配axis，下行索引初始化通过
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2025-04-29 11:59:00 +08:00 |
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Ruige Lee
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8ec52716a0
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带主机联调，slv1还没更新索引
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2025-04-28 18:01:16 +08:00 |
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Ruige Lee
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84cbe46dfa
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集合master 和slave 测试恢复
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2025-04-27 16:56:35 +08:00 |
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Ruige Lee
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4f8ee9466c
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临时切换
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2025-04-27 14:56:07 +08:00 |
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Ruige Lee
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7b63b07408
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现场基本恢复
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2025-04-25 17:00:51 +08:00 |
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Ruige Lee
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dc67286e23
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从站编译完成
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2025-04-24 17:31:44 +08:00 |
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Ruige Lee
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4013e19eda
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准备编译
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2025-04-24 16:18:33 +08:00 |
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Ruige Lee
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a555302c71
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SM sram化改造，探针改造，写接口
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2025-04-23 17:57:38 +08:00 |
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Ruige Lee
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7afd4a1249
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同步和probe写完
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2025-04-22 17:32:05 +08:00 |
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Ruige Lee
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58eb3c0aed
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处理顺序索引和同步
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2025-04-21 18:48:29 +08:00 |
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Ruige Lee
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3277e76e19
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接收SRAM指向SM单元
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2025-04-17 15:16:42 +08:00 |
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Ruige Lee
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19a23c9b16
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2k fifo抽出到顶层
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2025-04-17 10:55:00 +08:00 |
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Ruige Lee
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4962e217dd
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SM模块，即用4空位fifo控制的2KB fifo
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2025-04-16 16:50:36 +08:00 |
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Ruige Lee
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9cd2e7732b
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主站行为仅为axis到sram
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2025-04-16 16:49:42 +08:00 |
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Ruige Lee
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80739a1feb
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上行转发写入正确
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2025-04-14 17:53:04 +08:00 |
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Ruige Lee
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95b7f7b476
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下行写测试通过
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2025-04-14 17:24:53 +08:00 |
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Ruige Lee
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4552cc05db
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转发功能已经调通
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2025-04-14 16:43:10 +08:00 |
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Ruige Lee
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00a7b0fe6e
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基本功能单元编译通过，开始搭建测试环境校对流水线
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2025-04-11 17:57:47 +08:00 |
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Ruige Lee
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dabfc86983
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发送单元 接收单元代码收尾
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2025-04-09 17:29:57 +08:00 |
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Ruige Lee
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d7b04710ae
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框架开始收尾，协调流水线
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2025-04-08 17:29:45 +08:00 |
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Ruige Lee
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e34338753a
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从站收发框架已成
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2025-04-07 17:39:44 +08:00 |
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Ruige Lee
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703ad172b8
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下行报文载入寄存器
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2025-04-05 09:27:15 +08:00 |
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Ruige Lee
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5bc63aaee2
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建立从站状态机
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2025-04-03 17:49:33 +08:00 |
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Ruige Lee
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658d0d1ea2
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展开文件结构
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2025-04-02 16:40:25 +08:00 |
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Ruige Lee
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6c6cce1222
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CDRIn采样率改为8x，允许参数化
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2025-04-02 15:44:32 +08:00 |
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Ruige Lee
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eec4d5c18a
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高云FPGA：dout输出反相
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2025-03-18 15:46:16 +08:00 |
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Ruige Lee
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3c63a7accc
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高云FPGA：从站增加0.5s看门狗
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2025-03-17 17:32:25 +08:00 |
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