Ruige Lee
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706b9f17e5
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FPGA测试通过
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2025-08-27 17:06:31 +08:00 |
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Ruige Lee
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58ad17ce79
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修复
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2025-08-27 16:27:00 +08:00 |
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Ruige Lee
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bdabf08108
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Merge branch 'mp_eb_dev' into feature/clk3_shift_allow
# Conflicts:
# src/main/scala/backBoard/ebus/CDRIn.scala
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2025-08-27 14:59:39 +08:00 |
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Ruige Lee
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dd71c557b7
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Merge branch 'feature/liftCdr' into mp_eb_dev
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2025-08-27 14:45:29 +08:00 |
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Ruige Lee
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4e2e3f6ca4
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修复sync的64位加法器输入位宽转换问题
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2025-08-27 09:42:01 +08:00 |
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Ruige Lee
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4b90a2c9bd
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CDR拉到顶层
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2025-08-26 17:52:23 +08:00 |
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Ruige Lee
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c6bd7902e7
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Merge branch 'mp_eb_dev' into feature/liftCdr
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2025-08-26 17:07:58 +08:00 |
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Ruige Lee
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b821571218
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同步逻辑扩展delta位宽，使用分时共享64位加法器
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2025-08-26 17:02:57 +08:00 |
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Ruige Lee
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ae99f5801d
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spi读锁定0x118
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2025-08-26 15:17:37 +08:00 |
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Ruige Lee
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6b118fa498
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spi读0x100将会暂存后续寄存器防止进位
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2025-08-26 11:35:47 +08:00 |
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Ruige Lee
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72fe230200
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尝试把CDR提到顶层
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2025-08-26 10:30:12 +08:00 |
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Ruige Lee
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6f1101f6dc
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改异步复位，增加flush接口，删除其他工程代码以编译通过
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2025-08-25 19:16:27 +08:00 |
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Ruige Lee
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7dd8458f96
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允许正负3个cycle偏移
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2025-08-25 17:32:21 +08:00 |
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Ruige Lee
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bca9724c3c
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修改pllctrl复位默认值
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2025-08-25 14:30:15 +08:00 |
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Ruige Lee
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976c468b6a
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修改pllctrl复位默认值
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2025-08-25 11:41:53 +08:00 |
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Ruige Lee
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4df8ce5b84
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Merge branch 'mp_eb_dev' into feature/auto_release_insert
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2025-08-22 17:27:40 +08:00 |
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Ruige Lee
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b2da5cfb64
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清硬件错误中断多打一拍以优化cdrin的时序
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2025-08-22 17:26:52 +08:00 |
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Ruige Lee
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d2899df8b4
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看门狗目标寄存器初始值改为0xffffffff，看门狗计数器逻辑修改
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2025-08-22 15:38:51 +08:00 |
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Ruige Lee
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0a0a7a7712
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修正解锁条件
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2025-08-22 14:24:41 +08:00 |
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Ruige Lee
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06996d6945
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锁定后允许在正负3相位之间校准
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2025-08-21 18:57:28 +08:00 |
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Ruige Lee
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a20ee39087
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Merge branch 'mp_eb_dev' into feature/auto_release_insert
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2025-08-21 18:02:45 +08:00 |
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Ruige Lee
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cbca019a2b
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增加/修改模拟控制寄存器
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2025-08-20 19:30:49 +08:00 |
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Ruige Lee
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6d8edfd6ce
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锁定后，每16个cycle ，或许有bug
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2025-08-20 19:08:51 +08:00 |
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Ruige Lee
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0291d445ca
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Revert "cdrout 每128byte发送无意义“b0000000010”用于解锁cdrin并重新上锁"
This reverts commit d7146a786b.
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2025-08-20 15:40:25 +08:00 |
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Ruige Lee
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d7146a786b
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cdrout 每128byte发送无意义“b0000000010”用于解锁cdrin并重新上锁
需要配平fifo，覆盖每个长度端，长度边缘，解锁在crc位置，不同preamble长度
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2025-08-19 17:04:58 +08:00 |
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Ruige Lee
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946bbd8c35
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主站增加19号中断用于提示上行CRC错误
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2025-08-19 16:03:12 +08:00 |
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Ruige Lee
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827bbb2852
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修复主站CRC校验逻辑（欠一拍）；增加22号寄存器，提示主站接收CRC错误
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2025-08-19 15:19:21 +08:00 |
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Ruige Lee
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f3916df37b
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弃用高频率采样CDR的例化
Merge branch 'mp_eb_dev_多采样全表决' into mp_eb_dev
* mp_eb_dev_多采样全表决:
调整解锁条件为10个连续0
增加一个锁定可以暂时解决发送失败问题
滤波 表决 鉴相同时存在
enhance 要求先跨时钟，再进行后续表决
Revert "16相位改8相位"
16相位改8相位
bug: 16相位补充相 欠了一相
Revert "改6相位，从一个pll出，测试"
Revert "尝试3相位"
尝试3相位
改6相位，从一个pll出，测试
拉出测试IO
Revert "4多相位效果明显更好"
4多相位效果明显更好
16相位操作还是卡
# Conflicts:
# src/main/scala/backBoard/ebus/CDRIn.scala
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2025-08-19 10:00:25 +08:00 |
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Ruige Lee
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2fb450673f
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调整解锁条件为10个连续0
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2025-08-18 17:39:32 +08:00 |
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Ruige Lee
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2afd3f722a
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增加一个锁定可以暂时解决发送失败问题
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2025-08-18 16:20:50 +08:00 |
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Ruige Lee
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11bbf14226
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滤波 表决 鉴相同时存在
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2025-08-15 17:18:45 +08:00 |
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Ruige Lee
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45d2d223c1
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enhance 要求先跨时钟，再进行后续表决
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2025-08-15 15:28:28 +08:00 |
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Ruige Lee
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62684bd665
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Revert "16相位改8相位"
This reverts commit 2da45138db.
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2025-08-15 10:45:44 +08:00 |
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Ruige Lee
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2da45138db
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16相位改8相位
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2025-08-15 10:45:10 +08:00 |
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Ruige Lee
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fc917054ed
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bug: 16相位补充相 欠了一相
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2025-08-14 19:23:56 +08:00 |
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Ruige Lee
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573a1ad45f
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bug:滤波需要顺序打拍，防止边界上跳变
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2025-08-14 19:15:09 +08:00 |
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Ruige Lee
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035109bee1
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Revert "改6相位，从一个pll出，测试"
This reverts commit 495a238a26.
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2025-08-13 17:54:50 +08:00 |
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Ruige Lee
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4955b7a278
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Revert "尝试3相位"
This reverts commit c6aa7416fc.
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2025-08-13 17:54:39 +08:00 |
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Ruige Lee
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6c2f2fa93b
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主站必须发送大于8byte的包才会更新同步寄存器
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2025-08-13 15:39:00 +08:00 |
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Ruige Lee
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b97ce75c39
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Revert "从站只在同步包时更新自身时间信息"
This reverts commit 3f41920805.
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2025-08-13 11:40:19 +08:00 |
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Ruige Lee
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3f41920805
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从站只在同步包时更新自身时间信息
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2025-08-13 11:08:56 +08:00 |
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Ruige Lee
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c6aa7416fc
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尝试3相位
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2025-08-13 10:52:49 +08:00 |
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Ruige Lee
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495a238a26
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改6相位，从一个pll出，测试
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2025-08-13 10:00:11 +08:00 |
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Ruige Lee
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2a7faafcff
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修复位宽推断错误
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2025-08-12 18:09:40 +08:00 |
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Ruige Lee
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d045705950
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spi初始值改为1
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2025-08-12 17:54:24 +08:00 |
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Ruige Lee
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cb2c4f46e5
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拉出测试IO
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2025-08-12 17:48:35 +08:00 |
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Ruige Lee
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107895f6e0
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Revert "4多相位效果明显更好"
This reverts commit 7338314c17.
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2025-08-12 09:55:43 +08:00 |
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Ruige Lee
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7338314c17
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4多相位效果明显更好
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2025-08-11 19:33:56 +08:00 |
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Ruige Lee
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b0b221e8b0
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16相位操作还是卡
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2025-08-11 18:13:58 +08:00 |
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5448cfd23f
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增加顶层的FPGA上的sync输出,修改测试用例
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2025-08-11 18:04:46 +08:00 |
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