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Merge branch 'mp_eb_dev' into feature/auto_release_insert

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Ruige Lee
2025-08-22 17:27:40 +08:00
parent 0a0a7a7712 b2da5cfb64
commit 4df8ce5b84
7 changed files with 22 additions and 46 deletions
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10
src/main/scala/backBoard/shin/Interface.scala
View File

@@ -1060,10 +1060,10 @@ trait InterfaceWdt{ this: InterfaceBase =>
for( i <- 0 until 18 ){
cReg.wdtTarCnt(i) :=
Cat(
RegEnable( dataw, 0.U(8.W), isEnW & addrw === ( "h40b".U (16.W) + (4*i).U ) ),
RegEnable( dataw, 0.U(8.W), isEnW & addrw === ( "h40a".U (16.W) + (4*i).U ) ),
RegEnable( dataw, 0.U(8.W), isEnW & addrw === ( "h409".U (16.W) + (4*i).U ) ),
RegEnable( dataw, 0.U(8.W), isEnW & addrw === ( "h408".U (16.W) + (4*i).U ) ),
RegEnable( dataw, "hFF".U(8.W), isEnW & addrw === ( "h40b".U (16.W) + (4*i).U ) ),
RegEnable( dataw, "hFF".U(8.W), isEnW & addrw === ( "h40a".U (16.W) + (4*i).U ) ),
RegEnable( dataw, "hFF".U(8.W), isEnW & addrw === ( "h409".U (16.W) + (4*i).U ) ),
RegEnable( dataw, "hFF".U(8.W), isEnW & addrw === ( "h408".U (16.W) + (4*i).U ) ),
)
}
}
@@ -1201,7 +1201,7 @@ trait InterfaceSystem{ this: InterfaceBase =>
(io.intMstTrig(1) & cReg.intEnable(1)) | //主站接收完成
(isLocalSyncInt & cReg.intEnable(2)) | //主站发送周期到了
(isLatchEvent & cReg.intEnable(3)) | //latch Event
(~RegNext(isWdtTrigAndEnable, false.B) & isWdtTrigAndEnable & cReg.intEnable(4)) | //主站接收看门狗溢出
(isWdtTrigAndEnable & cReg.intEnable(4)) | //主站接收看门狗溢出
(0 until 8).map{ i => io.intSlvTrig(i) & cReg.intEnable(8+i)}.reduce(_|_) | //从站SM请求
(0 until 4).map{ i => io.intTransEnd(i) & cReg.intEnable(16+i)}.reduce(_|_) | //传输完成请求 16,17,18,19
isMstRecCRCErr | //override //主站状态下19为上行crc接收错误 //不会同时发生

17
src/main/scala/backBoard/shin/ShinTop.scala
View File

@@ -380,10 +380,10 @@ trait ShinTopSlave{ this: ShinTopBase =>
slaveParser.io.intHWClr(0) := interface.io.intHWTrig(0) & interface.io.intHWClr(0)
slaveParser.io.intHWClr(1) := interface.io.intHWTrig(1) & interface.io.intHWClr(1)
downCDRIn.reset := reset.asBool | ( interface.io.intHWTrig(0) & interface.io.intHWClr(0) )
upCDRIn.reset := reset.asBool | ( interface.io.intHWTrig(1) & interface.io.intHWClr(1) )
downCDROut.reset := reset.asBool | ( interface.io.intHWTrig(0) & interface.io.intHWClr(0) )
upCDROut.reset := reset.asBool | ( interface.io.intHWTrig(1) & interface.io.intHWClr(1) )
downCDRIn.reset := reset.asBool | RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) )
upCDRIn.reset := reset.asBool | RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) )
downCDROut.reset := reset.asBool | RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) )
upCDROut.reset := reset.asBool | RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) )
interface.io.lvds <> slaveParser.io.lvds
@@ -422,7 +422,7 @@ trait ShinTopWatchDog{ this: ShinTopBase =>
for( i <- 0 until 16 ){
when( isWdtSMEnable(i) & (wdtSMCnt(i) < interface.io.cReg.wdtTarCnt(i+1)) ){
wdtSMCnt(i) := wdtSMCnt(i) + 1.U
} .elsewhen( ~isWdtSMEnable(i) ){
} .elsewhen( ~isWdtSMEnable(i) || (wdtSMCnt(i) >= interface.io.cReg.wdtTarCnt(i+1)) ){
wdtSMCnt(i) := 0.U
}
@@ -446,7 +446,7 @@ trait ShinTopWatchDog{ this: ShinTopBase =>
when( isWdtRec2RtnEnable & (wdtRec2RtnCnt < interface.io.cReg.wdtTarCnt(0)) ){
wdtRec2RtnCnt := wdtRec2RtnCnt + 1.U
} .elsewhen( ~isWdtRec2RtnEnable ){
} .elsewhen( ~isWdtRec2RtnEnable || (wdtRec2RtnCnt >= interface.io.cReg.wdtTarCnt(0)) ){
wdtRec2RtnCnt := 0.U
}
@@ -460,8 +460,9 @@ trait ShinTopWatchDog{ this: ShinTopBase =>
when( interface.io.cReg.wdtEnable.extract(17) & (wdtRec2RecCnt < interface.io.cReg.wdtTarCnt(17)) ){
wdtRec2RecCnt := wdtRec2RecCnt + 1.U
} .elsewhen(
~interface.io.cReg.wdtEnable.extract(17) |
downCDRIn.io.axis.fire
~interface.io.cReg.wdtEnable.extract(17) ||
downCDRIn.io.axis.fire ||
(wdtRec2RecCnt >= interface.io.cReg.wdtTarCnt(17))
){
wdtRec2RecCnt := 0.U
}

8
src/main/scala/backBoard/shin/SlaveParser.scala
View File

@@ -991,11 +991,11 @@ with SlaveParserProbe{
io.intHWTrig(0) := downRecParser.io.isError
io.intHWTrig(1) := upRecParser.io.isError
downRecParser.reset := reset.asBool | (downRecParser.io.isError & io.intHWClr(0))
downSendGen.reset := reset.asBool | (downRecParser.io.isError & io.intHWClr(0))
downRecParser.reset := reset.asBool | RegNext(downRecParser.io.isError & io.intHWClr(0))
downSendGen.reset := reset.asBool | RegNext(downRecParser.io.isError & io.intHWClr(0))
upRecParser.reset := reset.asBool | (upRecParser.io.isError & io.intHWClr(1))
upSendGen.reset := reset.asBool | (upRecParser.io.isError & io.intHWClr(1))
upRecParser.reset := reset.asBool | RegNext(upRecParser.io.isError & io.intHWClr(1))
upSendGen.reset := reset.asBool | RegNext(upRecParser.io.isError & io.intHWClr(1))
io.downRecStat := downRecParser.io.stat
io.upRecStat := upRecParser.io.stat