RuigeLee
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46882b6b4d
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缩减后面积已经满足要求，时序违例，主要集中在alu和访存接口
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2024-10-31 17:38:12 +08:00 |
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RuigeLee
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7e99cf4489
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1SRAM加入仿真随机初始化；2CDR物理层重新对齐包头 3复制粘贴变量错误
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2024-10-17 15:32:16 +08:00 |
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RuigeLee
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d449980b5b
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物理层和链路层的包头一起合并处理
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2024-10-17 11:54:02 +08:00 |
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RuigeLee
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a6068fbda0
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新主站发送逻辑
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2024-10-09 17:37:15 +08:00 |
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RuigeLee
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753586a65e
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正确锁住，丢包率大
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2024-09-23 17:52:59 +08:00 |
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RuigeLee
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10b2e4c78f
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Revert "最后几个比特锁不住"
This reverts commit 97211f0962.
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2024-09-23 17:40:35 +08:00 |
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RuigeLee
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97211f0962
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最后几个比特锁不住
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2024-09-23 17:40:23 +08:00 |
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RuigeLee
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833ad07525
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采样头对齐问题，对齐哪个55和D5
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2024-09-23 17:23:34 +08:00 |
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RuigeLee
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6750593b48
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发送改用标志头锁时钟通道方案
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2024-09-23 16:44:44 +08:00 |
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RuigeLee
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3c357b54e0
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4倍频采3次
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2024-09-20 14:55:43 +08:00 |
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RuigeLee
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1368e9037d
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CDR基本测试通过
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2024-09-19 15:23:38 +08:00 |
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RuigeLee
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57c81d5cac
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CDRin编译通过
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2024-09-12 17:48:50 +08:00 |
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