Ruige Lee
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107895f6e0
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Revert "4多相位效果明显更好"
This reverts commit 7338314c17.
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2025-08-12 09:55:43 +08:00 |
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Ruige Lee
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7338314c17
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4多相位效果明显更好
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2025-08-11 19:33:56 +08:00 |
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Ruige Lee
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b0b221e8b0
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16相位操作还是卡
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2025-08-11 18:13:58 +08:00 |
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Ruige Lee
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1cb0cee966
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should >= 3
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2025-08-11 10:07:54 +08:00 |
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Ruige Lee
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a31b08dcda
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Merge branch 'mp_eb_dev' of github.com:whutddk/RISCV-MAC-SWICH into mp_eb_dev
# Conflicts:
# src/main/scala/backBoard/ebus/CDROut.scala
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2025-08-11 10:07:18 +08:00 |
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Ruige Lee
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cae503f4c2
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preamble应该大于3
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2025-08-11 10:05:49 +08:00 |
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RuigeLee
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424e07a076
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增加5选3多数表决滤波
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2025-08-09 22:22:19 +08:00 |
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1ce3840567
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PRE_NUM改为8后，功能正常
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2025-08-08 22:42:21 +08:00 |
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Ruige Lee
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dc4539124c
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可调preamble长度
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2025-08-07 17:39:11 +08:00 |
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Ruige Lee
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8c09a6c4aa
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写死16相位
Merge branch 'mp_eb_dev' into feature/multiPhaseCDRIn
# Conflicts:
# src/main/scala/backBoard/ebus/CDRIn.scala
# src/main/scala/backBoard/shin/ShinTop.scala
# tb/shinTest/ShinTopSpiTb.v
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2025-08-05 16:49:41 +08:00 |
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656986a8ab
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:Merge branch 'feature_shintop' into eb_dev
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2025-07-30 23:14:37 +08:00 |
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Ruige Lee
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8ba8ff0e9e
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**抹除**加密特性
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2025-07-30 15:36:18 +08:00 |
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Ruige Lee
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302893c3e7
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加入CDR的滤波，并修改测试led
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2025-07-28 14:31:45 +08:00 |
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Ruige Lee
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9f88d26ba1
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多相位时钟可以使用
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2025-07-22 11:49:33 +08:00 |
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Ruige Lee
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7c632c8c1b
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编译通过
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2025-07-22 09:35:06 +08:00 |
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Ruige Lee
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bf8fce2671
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需要考虑多项位时钟是按同步时钟还是异步时钟处理
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2025-07-17 17:47:59 +08:00 |
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Ruige Lee
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1319027c9e
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代码清理
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2025-07-17 17:22:08 +08:00 |
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Ruige Lee
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581c614017
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撤销idle状态cdrout强制传输线为0的设定
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2025-07-17 10:03:31 +08:00 |
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Ruige Lee
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cea2d01945
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使用rec的清中断复位sendGen模块；当CDRout的axis下溢，状态机回到IDLE
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2025-07-15 16:30:44 +08:00 |
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Ruige Lee
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370e6b119c
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处理断言及状态机卡住问题，从这个版本开始，所有断言错误都应该处理；recParser的错误状态会触发5、6号不可屏蔽中断，软件需要清中断然后recParser恢复状态，cdrout溢出问题不再触发中断，该次传输将会发生至少两次错误
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2025-05-26 11:52:40 +08:00 |
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Ruige Lee
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a4515146f7
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加密特性长度修复
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2025-05-22 17:28:31 +08:00 |
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Ruige Lee
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8f59ef55ac
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加密模块
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2025-05-22 16:54:17 +08:00 |
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Ruige Lee
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944255978a
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增加加密特性（未测试）
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2025-05-22 16:53:42 +08:00 |
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Ruige Lee
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4b2a52fa9b
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转发延迟缩减至126个cycle
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2025-05-20 11:35:11 +08:00 |
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Ruige Lee
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fb8bc91947
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暂时改回4倍采样以实现FPGA逻辑
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2025-05-13 17:05:38 +08:00 |
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Ruige Lee
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b55deb239f
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尝试速率配平，回环改到phy上
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2025-05-07 18:12:01 +08:00 |
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Ruige Lee
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19f4140dec
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尝试加入cdr模块，主站上行rsp， tlast还有亚稳态
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2025-05-06 17:39:52 +08:00 |
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Ruige Lee
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dabfc86983
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发送单元 接收单元代码收尾
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2025-04-09 17:29:57 +08:00 |
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Ruige Lee
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6c6cce1222
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CDRIn采样率改为8x，允许参数化
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2025-04-02 15:44:32 +08:00 |
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Ruige Lee
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bcb1c8e8f3
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修改指令编号
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2025-03-04 14:45:31 +08:00 |
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Ruige Lee
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46cbd6edec
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rxFifo bypass to txFifo
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2025-03-04 12:01:47 +08:00 |
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Ruige Lee
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1c7eb4ce47
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使用未使用4b/5b编码作为preamble
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2025-03-04 10:58:59 +08:00 |
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Ruige Lee
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9937485831
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bug修复：定义CDR清中断和中断到来同时发生的行为
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2025-02-27 17:27:15 +08:00 |
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Ruige Lee
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ea6ea66040
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文件结构调整
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2025-02-26 15:36:57 +08:00 |
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Ruige Lee
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598982cc95
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加入中断寄存器，加入两个32bits寄存器
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2025-02-20 19:04:30 +08:00 |
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Ruige Lee (WSL)
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522d7c19c6
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try RoCC
hack 入，但io如何扇出到顶层？
Revert "hack 入，但io如何扇出到顶层？"
This reverts commit 04dd4dff462b8986d18d13ee7c6b3f17caad247c.
Revert "Revert "hack 入，但io如何扇出到顶层？""
This reverts commit a2fadc0e5524cd292ed245f1fbb5f4a688d95a1d.
CDRIN成功扇出
Rocc仿真环境
扇出RoCC请求返回的FIFO
Revert "扇出RoCC请求返回的FIFO"
This reverts commit c52777091403d300f19935df7b6de3d62c57430b.
RoCC请求返回FIFO使用FLOW模式
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2025-02-20 15:29:04 +08:00 |
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Ruige Lee
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6eaaebafcc
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fifo空间剩余
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2025-02-12 16:50:07 +08:00 |
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Ruige Lee
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d7effd7543
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修正tl2cdr status寄存器访问错误
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2025-02-11 17:32:08 +08:00 |
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Ruige Lee
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ecff635e83
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删除CDR中的硬件CDR
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2025-02-11 15:17:02 +08:00 |
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Ruige Lee
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94acbfae03
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对FSMC的外部IO仿真接线
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2025-02-10 11:17:39 +08:00 |
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fd74e07123
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暂时屏蔽了fsmc两个诊断宏，便于调试；增加汇编代码，已经看到Tx0作为下行输出的波形了
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2025-02-09 20:08:14 +08:00 |
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Ruige Lee
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55675b93c9
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txfinish转换为txfinish，同频模式有效
加入发送接收中断
cdr模块例化代码规范化
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2025-02-08 16:28:42 +08:00 |
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Ruige Lee
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1b4243b14d
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FSMC模块
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2025-02-08 15:46:49 +08:00 |
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Ruige Lee
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a00223ef8f
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4个CDR上下行分离
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2025-02-05 18:06:52 +08:00 |
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Ruige Lee
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313b7cc11b
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增加CDR的约束定时器
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2025-01-27 22:26:26 +08:00 |
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Ruige Lee
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b75e724948
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加入外置CRC32_32
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2025-01-24 16:01:10 +08:00 |
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Ruige Lee (WSL)
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33f2160365
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修复错误位宽，加入islast
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2025-01-17 16:21:46 +08:00 |
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Ruige Lee (WSL)
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bf0e345cc9
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tl2cdr增加附带io
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2025-01-16 17:57:44 +08:00 |
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Ruige Lee
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981b492a8b
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接入TL2CDR
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2025-01-10 15:25:10 +08:00 |
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Ruige Lee (WSL)
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134440812b
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compile without tl2cdr
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2025-01-09 19:10:07 +08:00 |
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