Ruige Lee
|
0291d445ca
|
Revert "cdrout 每128byte发送无意义“b0000000010”用于解锁cdrin并重新上锁"
This reverts commit d7146a786b.
|
2025-08-20 15:40:25 +08:00 |
|
Ruige Lee
|
d7146a786b
|
cdrout 每128byte发送无意义“b0000000010”用于解锁cdrin并重新上锁
需要配平fifo，覆盖每个长度端，长度边缘，解锁在crc位置，不同preamble长度
|
2025-08-19 17:04:58 +08:00 |
|
Ruige Lee
|
f3916df37b
|
弃用高频率采样CDR的例化
Merge branch 'mp_eb_dev_多采样全表决' into mp_eb_dev
* mp_eb_dev_多采样全表决:
调整解锁条件为10个连续0
增加一个锁定可以暂时解决发送失败问题
滤波 表决 鉴相同时存在
enhance 要求先跨时钟，再进行后续表决
Revert "16相位改8相位"
16相位改8相位
bug: 16相位补充相 欠了一相
Revert "改6相位，从一个pll出，测试"
Revert "尝试3相位"
尝试3相位
改6相位，从一个pll出，测试
拉出测试IO
Revert "4多相位效果明显更好"
4多相位效果明显更好
16相位操作还是卡
# Conflicts:
# src/main/scala/backBoard/ebus/CDRIn.scala
|
2025-08-19 10:00:25 +08:00 |
|
Ruige Lee
|
2fb450673f
|
调整解锁条件为10个连续0
|
2025-08-18 17:39:32 +08:00 |
|
Ruige Lee
|
2afd3f722a
|
增加一个锁定可以暂时解决发送失败问题
|
2025-08-18 16:20:50 +08:00 |
|
Ruige Lee
|
11bbf14226
|
滤波 表决 鉴相同时存在
|
2025-08-15 17:18:45 +08:00 |
|
Ruige Lee
|
45d2d223c1
|
enhance 要求先跨时钟，再进行后续表决
|
2025-08-15 15:28:28 +08:00 |
|
Ruige Lee
|
62684bd665
|
Revert "16相位改8相位"
This reverts commit 2da45138db.
|
2025-08-15 10:45:44 +08:00 |
|
Ruige Lee
|
2da45138db
|
16相位改8相位
|
2025-08-15 10:45:10 +08:00 |
|
Ruige Lee
|
fc917054ed
|
bug: 16相位补充相 欠了一相
|
2025-08-14 19:23:56 +08:00 |
|
Ruige Lee
|
573a1ad45f
|
bug:滤波需要顺序打拍，防止边界上跳变
|
2025-08-14 19:15:09 +08:00 |
|
Ruige Lee
|
035109bee1
|
Revert "改6相位，从一个pll出，测试"
This reverts commit 495a238a26.
|
2025-08-13 17:54:50 +08:00 |
|
Ruige Lee
|
4955b7a278
|
Revert "尝试3相位"
This reverts commit c6aa7416fc.
|
2025-08-13 17:54:39 +08:00 |
|
Ruige Lee
|
c6aa7416fc
|
尝试3相位
|
2025-08-13 10:52:49 +08:00 |
|
Ruige Lee
|
495a238a26
|
改6相位，从一个pll出，测试
|
2025-08-13 10:00:11 +08:00 |
|
Ruige Lee
|
cb2c4f46e5
|
拉出测试IO
|
2025-08-12 17:48:35 +08:00 |
|
Ruige Lee
|
107895f6e0
|
Revert "4多相位效果明显更好"
This reverts commit 7338314c17.
|
2025-08-12 09:55:43 +08:00 |
|
Ruige Lee
|
7338314c17
|
4多相位效果明显更好
|
2025-08-11 19:33:56 +08:00 |
|
Ruige Lee
|
b0b221e8b0
|
16相位操作还是卡
|
2025-08-11 18:13:58 +08:00 |
|
Ruige Lee
|
1cb0cee966
|
should >= 3
|
2025-08-11 10:07:54 +08:00 |
|
Ruige Lee
|
a31b08dcda
|
Merge branch 'mp_eb_dev' of github.com:whutddk/RISCV-MAC-SWICH into mp_eb_dev
# Conflicts:
# src/main/scala/backBoard/ebus/CDROut.scala
|
2025-08-11 10:07:18 +08:00 |
|
Ruige Lee
|
cae503f4c2
|
preamble应该大于3
|
2025-08-11 10:05:49 +08:00 |
|
RuigeLee
|
424e07a076
|
增加5选3多数表决滤波
|
2025-08-09 22:22:19 +08:00 |
|
|
|
1ce3840567
|
PRE_NUM改为8后，功能正常
|
2025-08-08 22:42:21 +08:00 |
|
Ruige Lee
|
dc4539124c
|
可调preamble长度
|
2025-08-07 17:39:11 +08:00 |
|
Ruige Lee
|
8c09a6c4aa
|
写死16相位
Merge branch 'mp_eb_dev' into feature/multiPhaseCDRIn
# Conflicts:
# src/main/scala/backBoard/ebus/CDRIn.scala
# src/main/scala/backBoard/shin/ShinTop.scala
# tb/shinTest/ShinTopSpiTb.v
|
2025-08-05 16:49:41 +08:00 |
|
|
|
656986a8ab
|
:Merge branch 'feature_shintop' into eb_dev
|
2025-07-30 23:14:37 +08:00 |
|
Ruige Lee
|
8ba8ff0e9e
|
**抹除**加密特性
|
2025-07-30 15:36:18 +08:00 |
|
Ruige Lee
|
302893c3e7
|
加入CDR的滤波，并修改测试led
|
2025-07-28 14:31:45 +08:00 |
|
Ruige Lee
|
9f88d26ba1
|
多相位时钟可以使用
|
2025-07-22 11:49:33 +08:00 |
|
Ruige Lee
|
7c632c8c1b
|
编译通过
|
2025-07-22 09:35:06 +08:00 |
|
Ruige Lee
|
bf8fce2671
|
需要考虑多项位时钟是按同步时钟还是异步时钟处理
|
2025-07-17 17:47:59 +08:00 |
|
Ruige Lee
|
1319027c9e
|
代码清理
|
2025-07-17 17:22:08 +08:00 |
|
Ruige Lee
|
581c614017
|
撤销idle状态cdrout强制传输线为0的设定
|
2025-07-17 10:03:31 +08:00 |
|
Ruige Lee
|
cea2d01945
|
使用rec的清中断复位sendGen模块；当CDRout的axis下溢，状态机回到IDLE
|
2025-07-15 16:30:44 +08:00 |
|
Ruige Lee
|
370e6b119c
|
处理断言及状态机卡住问题，从这个版本开始，所有断言错误都应该处理；recParser的错误状态会触发5、6号不可屏蔽中断，软件需要清中断然后recParser恢复状态，cdrout溢出问题不再触发中断，该次传输将会发生至少两次错误
|
2025-05-26 11:52:40 +08:00 |
|
Ruige Lee
|
a4515146f7
|
加密特性长度修复
|
2025-05-22 17:28:31 +08:00 |
|
Ruige Lee
|
8f59ef55ac
|
加密模块
|
2025-05-22 16:54:17 +08:00 |
|
Ruige Lee
|
944255978a
|
增加加密特性（未测试）
|
2025-05-22 16:53:42 +08:00 |
|
Ruige Lee
|
4b2a52fa9b
|
转发延迟缩减至126个cycle
|
2025-05-20 11:35:11 +08:00 |
|
Ruige Lee
|
fb8bc91947
|
暂时改回4倍采样以实现FPGA逻辑
|
2025-05-13 17:05:38 +08:00 |
|
Ruige Lee
|
b55deb239f
|
尝试速率配平，回环改到phy上
|
2025-05-07 18:12:01 +08:00 |
|
Ruige Lee
|
19f4140dec
|
尝试加入cdr模块，主站上行rsp， tlast还有亚稳态
|
2025-05-06 17:39:52 +08:00 |
|
Ruige Lee
|
dabfc86983
|
发送单元 接收单元代码收尾
|
2025-04-09 17:29:57 +08:00 |
|
Ruige Lee
|
6c6cce1222
|
CDRIn采样率改为8x，允许参数化
|
2025-04-02 15:44:32 +08:00 |
|
Ruige Lee
|
bcb1c8e8f3
|
修改指令编号
|
2025-03-04 14:45:31 +08:00 |
|
Ruige Lee
|
46cbd6edec
|
rxFifo bypass to txFifo
|
2025-03-04 12:01:47 +08:00 |
|
Ruige Lee
|
1c7eb4ce47
|
使用未使用4b/5b编码作为preamble
|
2025-03-04 10:58:59 +08:00 |
|
Ruige Lee
|
9937485831
|
bug修复：定义CDR清中断和中断到来同时发生的行为
|
2025-02-27 17:27:15 +08:00 |
|
Ruige Lee
|
ea6ea66040
|
文件结构调整
|
2025-02-26 15:36:57 +08:00 |
|
