拆分CDRIn为采样部分和axis部分;调整层次结构,仅将cdrInSample放在顶层;放置3组CDRInSample,使用寄存器选择

This commit is contained in:
RuigeLee
2025-09-06 11:07:41 +08:00
parent ac118289b2
commit ff7aba38ad
4 changed files with 179 additions and 113 deletions

View File

@@ -20,7 +20,9 @@ class SimCDR extends Module with RequireAsyncReset{
val cdrIn = Module(new MPCDRIn)
val cdrInAxis = Module(new CDRInAxis)
val cdrInSample = Module(new CDRInMultiSample)
val cdrOut = Module(new CDROut)
val record = Module( new Queue(UInt(8.W), 256) )
@@ -52,11 +54,14 @@ class SimCDR extends Module with RequireAsyncReset{
cdrOut.io.flush := io.flush
cdrIn.clock := io.multiCLK(0).asClock
cdrIn.io.flush := io.flush
cdrIn.multiCLK := io.multiCLK
cdrInAxis.clock := io.multiCLK(0).asClock
cdrInSample.clock := io.multiCLK(0).asClock
cdrInAxis.io.flush := io.flush
cdrInSample.multiCLK := io.multiCLK
cdrInAxis.io.syncSerDat := cdrInSample.io.syncSerDat
cdrIn.io.serDat := cdrOut.io.serDat
cdrInSample.io.serDat := cdrOut.io.serDat
assert( ~(record.io.enq.valid & ~record.io.enq.ready), "Assert Failed, Warning, fifo overflow!\n" )
assert( ~(~record.io.deq.valid & record.io.deq.ready), "Assert Failed, Warning, fifo underflow!\n" )
@@ -73,11 +78,11 @@ class SimCDR extends Module with RequireAsyncReset{
record.io.enq.valid := cdrOut.io.axis.fire
record.io.enq.bits := io.data
record.io.deq.ready := cdrIn.io.axis.fire
cdrIn.io.axis.ready := true.B
record.io.deq.ready := cdrInAxis.io.axis.fire
cdrInAxis.io.axis.ready := true.B
io.isFailed := cdrIn.io.axis.fire & (record.io.deq.bits =/= cdrIn.io.axis.bits.tdata)
io.isSuccess := cdrIn.io.axis.fire & cdrIn.io.axis.bits.tlast
io.isFailed := cdrInAxis.io.axis.fire & (record.io.deq.bits =/= cdrInAxis.io.axis.bits.tdata)
io.isSuccess := cdrInAxis.io.axis.fire & cdrInAxis.io.axis.bits.tlast
@@ -87,14 +92,14 @@ class SimCDR extends Module with RequireAsyncReset{
when( isUsing8b10b ){
b8b10Encoder.io <> cdrOut.io.encode
b8b10Decoder.io <> cdrIn.io.decode
b8b10Decoder.io <> cdrInAxis.io.decode
b4b5Encoder.io.isEnable := false.B
b4b5Encoder.io.dataIn := 0.U
b4b5Decoder.io.dataIn := 0.U
} .otherwise{
b4b5Encoder.io <> cdrOut.io.encode
b4b5Decoder.io <> cdrIn.io.decode
b4b5Decoder.io <> cdrInAxis.io.decode
b8b10Encoder.io.isEnable := false.B
b8b10Encoder.io.dataIn := 0.U