From ff7aba38ad79ef19824c14781b59bd87708c6316 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Sat, 6 Sep 2025 11:07:41 +0800 Subject: [PATCH] =?UTF-8?q?=E6=8B=86=E5=88=86CDRIn=E4=B8=BA=E9=87=87?= =?UTF-8?q?=E6=A0=B7=E9=83=A8=E5=88=86=E5=92=8Caxis=E9=83=A8=E5=88=86?= =?UTF-8?q?=EF=BC=9B=E8=B0=83=E6=95=B4=E5=B1=82=E6=AC=A1=E7=BB=93=E6=9E=84?= =?UTF-8?q?=EF=BC=8C=E4=BB=85=E5=B0=86cdrInSample=E6=94=BE=E5=9C=A8?= =?UTF-8?q?=E9=A1=B6=E5=B1=82=EF=BC=9B=E6=94=BE=E7=BD=AE3=E7=BB=84CDRInSam?= =?UTF-8?q?ple=EF=BC=8C=E4=BD=BF=E7=94=A8=E5=AF=84=E5=AD=98=E5=99=A8?= =?UTF-8?q?=E9=80=89=E6=8B=A9?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/ebus/CDRIn.scala | 43 ++--- .../scala/backBoard/shin/MstSlvSwitch.scala | 180 +++++++++++------- src/main/scala/backBoard/shin/ShinTop.scala | 42 ++-- src/test/scala/SimCDR.scala | 27 +-- 4 files changed, 179 insertions(+), 113 deletions(-) diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala index fa1d810..37b997d 100644 --- a/src/main/scala/backBoard/ebus/CDRIn.scala +++ b/src/main/scala/backBoard/ebus/CDRIn.scala @@ -5,34 +5,17 @@ import chisel3.util._ - - - -//work in 100MHZ -class CDRInIO extends Bundle{ - val axis = Decoupled(new AXIS_Bundle(8)) - val decode = Flipped(new Decode_Bundle) +class CDRInSampleIO extends Bundle{ val serDat = Input(Bool()) - val flush = Input(Bool()) + val syncSerDat = Output(Bool()) } - - -abstract class CDRInBase extends Module with RequireAsyncReset{ - val io: CDRInIO = IO(new CDRInIO) - io.decode.dataIn := 0.U - - val syncSerDat = Wire(Bool()) -} - - -trait CDRInMultiSample{ this: CDRInBase => - +class CDRInMultiSample extends Module with RequireAsyncReset{ + val io: CDRInSampleIO = IO(new CDRInSampleIO) val clkNum: Int = 16 require( clkNum == 16 ) - //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先 val multiCLK = IO(Input(Vec(clkNum, Bool()))) @@ -196,14 +179,22 @@ trait CDRInMultiSample{ this: CDRInBase => ) - syncSerDat := asyncSerDat + io.syncSerDat := asyncSerDat } +class CDRInAxisIO extends Bundle{ + val axis = Decoupled(new AXIS_Bundle(8)) + val decode = Flipped(new Decode_Bundle) + val syncSerDat = Input(Bool()) + val flush = Input(Bool()) +} -trait CDRInAxis{ this: CDRInBase => +class CDRInAxis extends Module with RequireAsyncReset{ + val io: CDRInAxisIO = IO(new CDRInAxisIO) + io.decode.dataIn := 0.U def HeaderByte: Int = 4 val ETH_PRE = "h68".U(8.W) @@ -224,7 +215,7 @@ trait CDRInAxis{ this: CDRInBase => when( io.flush ){ checkSFD := 0.U } .otherwise{ - checkSFD := Cat( checkSFD(8,0), syncSerDat ) + checkSFD := Cat( checkSFD(8,0), io.syncSerDat ) } io.decode.dataIn := checkSFD(9,0) @@ -310,7 +301,5 @@ trait CDRInAxis{ this: CDRInBase => } -class MPCDRIn extends CDRInBase -with CDRInAxis -with CDRInMultiSample + diff --git a/src/main/scala/backBoard/shin/MstSlvSwitch.scala b/src/main/scala/backBoard/shin/MstSlvSwitch.scala index f0efcdc..47c515d 100644 --- a/src/main/scala/backBoard/shin/MstSlvSwitch.scala +++ b/src/main/scala/backBoard/shin/MstSlvSwitch.scala @@ -38,12 +38,8 @@ class TopBase_IO_Bundle extends Bundle{ class MstSlvSwitchIO extends TopBase_IO_Bundle{ - - val downCDROut = Flipped(new CDROutIO) - val upCDROut = Flipped(new CDROutIO) - val downCDRIn = Flipped(new CDRInIO) - val upCDRIn = Flipped(new CDRInIO) - + val downCDRSampleIn = Vec(3, Flipped(new CDRInSampleIO) ) + val upCDRSampleIn = Vec(3, Flipped(new CDRInSampleIO) ) } @@ -55,6 +51,12 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{ val io: MstSlvSwitchIO = IO(new MstSlvSwitchIO) + val downCDROut = Module(new CDROut) + val upCDROut = Module(new CDROut) + + val downCDRInAxis = Module(new CDRInAxis) + val upCDRInAxis = Module(new CDRInAxis) + val slaveParser = Module(new SlaveParser ) val masterParser = Module(new MasterParser) @@ -68,17 +70,26 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{ val b8b10UpEncoder = Module(new b8b10Encode) val b8b10UpDecoder = Module(new b8b10Decode) - val interface = Module(new Interface) + val downInSerDat = Wire(Bool()) + val downInSyncSerDat = Wire(Bool()); downCDRInAxis.io.syncSerDat := downInSyncSerDat + val upInSerDat = Wire(Bool()) + val upInSyncSerDat = Wire(Bool()); upCDRInAxis.io.syncSerDat := upInSyncSerDat + + dontTouch(downInSerDat) + dontTouch(downInSyncSerDat) + dontTouch(upInSerDat) + dontTouch(upInSyncSerDat) + interface.io.latchPin := io.latchPin interface.io.uniCode := io.uniCode interface.io.hwSerial := io.hwSerial - interface.io.intTransEnd(0) := io.downCDRIn.axis.fire & io.downCDRIn.axis.bits.tlast - interface.io.intTransEnd(1) := io.downCDROut.axis.fire & io.downCDROut.axis.bits.tlast - interface.io.intTransEnd(2) := io.upCDRIn.axis.fire & io.upCDRIn.axis.bits.tlast - interface.io.intTransEnd(3) := io.upCDROut.axis.fire & io.upCDROut.axis.bits.tlast + interface.io.intTransEnd(0) := downCDRInAxis.io.axis.fire & downCDRInAxis.io.axis.bits.tlast + interface.io.intTransEnd(1) := downCDROut.io.axis.fire & downCDROut.io.axis.bits.tlast + interface.io.intTransEnd(2) := upCDRInAxis.io.axis.fire & upCDRInAxis.io.axis.bits.tlast + interface.io.intTransEnd(3) := upCDROut.io.axis.fire & upCDROut.io.axis.bits.tlast io.isSoftReset := interface.io.isSoftReset io.interrupt := interface.io.interrupt @@ -239,24 +250,24 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{ slaveParser.io.sram_r(3).datar := 0.U masterParser.io.sram_r.datar := 0.U - io.downCDRIn.axis.ready := false.B + downCDRInAxis.io.axis.ready := false.B slaveParser.io.downIn.valid := false.B slaveParser.io.downIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) slaveParser.io.downOut.ready := false.B masterParser.io.downOut.ready := false.B - io.downCDROut.axis.valid := false.B - io.downCDROut.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) + downCDROut.io.axis.valid := false.B + downCDROut.io.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) - io.upCDRIn.axis.ready := false.B + upCDRInAxis.io.axis.ready := false.B slaveParser.io.upIn.valid := false.B slaveParser.io.upIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) masterParser.io.upIn.valid := false.B masterParser.io.upIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) slaveParser.io.upOut.ready := false.B - io.upCDROut.axis.valid := false.B - io.upCDROut.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) + upCDROut.io.axis.valid := false.B + upCDROut.io.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) interface.io.mstDeltaTime := 0.U @@ -287,8 +298,8 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{ trait MstSlvSwitchMaster{ this: MstSlvSwitchBase => when( interface.io.cReg.modeSel === true.B ){ - masterParser.io.downOut <> io.downCDROut.axis - masterParser.io.upIn <> io.upCDRIn.axis + masterParser.io.downOut <> downCDROut.io.axis + masterParser.io.upIn <> upCDRInAxis.io.axis } when( interface.io.cReg.modeSel === true.B ){ @@ -355,10 +366,10 @@ trait MstSlvSwitchMaster{ this: MstSlvSwitchBase => trait MstSlvSwitchSlave{ this: MstSlvSwitchBase => when( interface.io.cReg.modeSel === false.B ){ - slaveParser.io.downIn <> io.downCDRIn.axis - io.downCDROut.axis <> slaveParser.io.downOut - slaveParser.io.upIn <> io.upCDRIn.axis - io.upCDROut.axis <> slaveParser.io.upOut + slaveParser.io.downIn <> downCDRInAxis.io.axis + downCDROut.io.axis <> slaveParser.io.downOut + slaveParser.io.upIn <> upCDRInAxis.io.axis + upCDROut.io.axis <> slaveParser.io.upOut } slaveParser.io.cReg := interface.io.cReg @@ -419,10 +430,10 @@ trait MstSlvSwitchSlave{ this: MstSlvSwitchBase => slaveParser.io.intHWClr(0) := interface.io.intHWTrig(0) & interface.io.intHWClr(0) slaveParser.io.intHWClr(1) := interface.io.intHWTrig(1) & interface.io.intHWClr(1) - io.downCDRIn.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0), false.B ) - io.upCDRIn.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1), false.B ) - io.downCDROut.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0), false.B ) - io.upCDROut.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1), false.B ) + downCDRInAxis.io.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0), false.B ) + upCDRInAxis.io.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1), false.B ) + downCDROut.io.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0), false.B ) + upCDROut.io.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1), false.B ) interface.io.lvds <> slaveParser.io.lvds @@ -475,11 +486,11 @@ trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase => val wdtRec2RtnCnt = RegInit(0.U(32.W)) when( - (io.upCDRIn.axis.fire & io.upCDRIn.axis.bits.tlast) | + (upCDRInAxis.io.axis.fire & upCDRInAxis.io.axis.bits.tlast) | ~interface.io.cReg.wdtEnable.extract(0) ){ isWdtRec2RtnEnable := false.B - } .elsewhen( ~isWdtRec2RtnEnable & io.downCDROut.axis.fire & interface.io.cReg.wdtEnable.extract(0) ){ + } .elsewhen( ~isWdtRec2RtnEnable & downCDROut.io.axis.fire & interface.io.cReg.wdtEnable.extract(0) ){ isWdtRec2RtnEnable := true.B } @@ -500,7 +511,7 @@ trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase => wdtRec2RecCnt := wdtRec2RecCnt + 1.U } .elsewhen( ~interface.io.cReg.wdtEnable.extract(17) || - io.downCDRIn.axis.fire || + downCDRInAxis.io.axis.fire || (wdtRec2RecCnt >= interface.io.cReg.wdtTarCnt(17)) ){ wdtRec2RecCnt := 0.U @@ -516,8 +527,8 @@ trait MstSlvSwitchDataPath{ this: MstSlvSwitchBase => when( ~isDwUpEx ){ //未交叉 when( interface.io.cReg.modeSel === false.B ){ //slave when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误 - io.downCDRIn.serDat := false.B - io.upCDRIn.serDat := false.B + downInSerDat := false.B + upInSerDat := false.B when( slaveParser.io.isLoop ){ //回环 io.dDatOut := false.B io.uDatOut := io.dDatIn @@ -527,21 +538,21 @@ trait MstSlvSwitchDataPath{ this: MstSlvSwitchBase => } } .otherwise{ //无硬件错误 when( slaveParser.io.isLoop ){ //回环 - io.downCDRIn.serDat := io.dDatIn - io.upCDRIn.serDat := io.downCDROut.serDat + downInSerDat := io.dDatIn + upInSerDat := downCDROut.io.serDat io.dDatOut := false.B - io.uDatOut := io.upCDROut.serDat + io.uDatOut := upCDROut.io.serDat } .otherwise{ //非回环 - io.downCDRIn.serDat := io.dDatIn - io.upCDRIn.serDat := io.uDatIn - io.dDatOut := io.downCDROut.serDat - io.uDatOut := io.upCDROut.serDat + downInSerDat := io.dDatIn + upInSerDat := io.uDatIn + io.dDatOut := downCDROut.io.serDat + io.uDatOut := upCDROut.io.serDat } } } .otherwise{ //master - io.downCDRIn.serDat := false.B - io.upCDRIn.serDat := io.uDatIn - io.dDatOut := io.downCDROut.serDat + downInSerDat := false.B + upInSerDat := io.uDatIn + io.dDatOut := downCDROut.io.serDat io.uDatOut := false.B } } .otherwise{ //交叉 @@ -551,31 +562,31 @@ trait MstSlvSwitchDataPath{ this: MstSlvSwitchBase => when( slaveParser.io.isLoop ){ //回环 io.dDatOut := io.uDatIn io.uDatOut := false.B - io.downCDRIn.serDat := false.B - io.upCDRIn.serDat := false.B + downInSerDat := false.B + upInSerDat := false.B } .otherwise{ //非回环 io.dDatOut := io.dDatIn io.uDatOut := io.uDatIn - io.downCDRIn.serDat := false.B - io.upCDRIn.serDat := false.B + downInSerDat := false.B + upInSerDat := false.B } } .otherwise{ //无硬件错误 when( slaveParser.io.isLoop ){ //回环 - io.downCDRIn.serDat := io.uDatIn - io.upCDRIn.serDat := io.downCDROut.serDat + downInSerDat := io.uDatIn + upInSerDat := downCDROut.io.serDat io.uDatOut := false.B - io.dDatOut := io.upCDROut.serDat + io.dDatOut := upCDROut.io.serDat } .otherwise{ //非回环 - io.downCDRIn.serDat := io.uDatIn - io.upCDRIn.serDat := io.dDatIn - io.dDatOut := io.upCDROut.serDat - io.uDatOut := io.downCDROut.serDat + downInSerDat := io.uDatIn + upInSerDat := io.dDatIn + io.dDatOut := upCDROut.io.serDat + io.uDatOut := downCDROut.io.serDat } } } .otherwise{ //master - io.downCDRIn.serDat := false.B - io.upCDRIn.serDat := io.dDatIn - io.uDatOut := io.downCDROut.serDat + downInSerDat := false.B + upInSerDat := io.dDatIn + io.uDatOut := downCDROut.io.serDat io.dDatOut := false.B } } @@ -585,10 +596,10 @@ trait MstSlvSwitchB8B4{ this: MstSlvSwitchBase => val isUsing8b10b = interface.io.cReg.b8b4Sel.extract(0) when( isUsing8b10b ){ - b8b10DownEncoder.io <> io.downCDROut.encode - b8b10DownDecoder.io <> io.downCDRIn.decode - b8b10UpEncoder.io <> io.upCDROut.encode - b8b10UpDecoder.io <> io.upCDRIn.decode + b8b10DownEncoder.io <> downCDROut.io.encode + b8b10DownDecoder.io <> downCDRInAxis.io.decode + b8b10UpEncoder.io <> upCDROut.io.encode + b8b10UpDecoder.io <> upCDRInAxis.io.decode b4b5DownEncoder.io.isEnable := false.B b4b5DownEncoder.io.dataIn := 0.U @@ -597,10 +608,10 @@ trait MstSlvSwitchB8B4{ this: MstSlvSwitchBase => b4b5UpEncoder.io.dataIn := 0.U b4b5UpDecoder.io.dataIn := 0.U } .otherwise{ - b4b5DownEncoder.io <> io.downCDROut.encode - b4b5DownDecoder.io <> io.downCDRIn.decode - b4b5UpEncoder.io <> io.upCDROut.encode - b4b5UpDecoder.io <> io.upCDRIn.decode + b4b5DownEncoder.io <> downCDROut.io.encode + b4b5DownDecoder.io <> downCDRInAxis.io.decode + b4b5UpEncoder.io <> upCDROut.io.encode + b4b5UpDecoder.io <> upCDRInAxis.io.decode b8b10DownEncoder.io.isEnable := false.B b8b10DownEncoder.io.dataIn := 0.U @@ -615,6 +626,47 @@ trait MstSlvSwitchCDRIn{ this: MstSlvSwitchBase => val cdrSelB = interface.io.cReg.cdrParam === 1.U val cdrSelC = interface.io.cReg.cdrParam === 2.U val cdrSelA = ~cdrSelB & ~cdrSelC + + // val downCDRSampleIn = Vec(3, Flipped(new CDRInSampleIO) ) + // val upCDRSampleIn = Vec(3, Flipped(new CDRInSampleIO) ) + + + + + when(cdrSelB){ + io.downCDRSampleIn(1).serDat := downInSerDat + io.upCDRSampleIn(1).serDat := downInSerDat + downInSyncSerDat := io.downCDRSampleIn(1).syncSerDat + upInSyncSerDat := io.upCDRSampleIn(1).syncSerDat + + io.downCDRSampleIn(0).serDat := false.B + io.upCDRSampleIn(0).serDat := false.B + io.downCDRSampleIn(2).serDat := false.B + io.upCDRSampleIn(2).serDat := false.B + } .elsewhen(cdrSelC){ + io.downCDRSampleIn(2).serDat := downInSerDat + io.upCDRSampleIn(2).serDat := downInSerDat + downInSyncSerDat := io.downCDRSampleIn(2).syncSerDat + upInSyncSerDat := io.upCDRSampleIn(2).syncSerDat + + io.downCDRSampleIn(0).serDat := false.B + io.upCDRSampleIn(0).serDat := false.B + io.downCDRSampleIn(1).serDat := false.B + io.upCDRSampleIn(1).serDat := false.B + } .otherwise{ + io.downCDRSampleIn(0).serDat := downInSerDat + io.upCDRSampleIn(0).serDat := downInSerDat + downInSyncSerDat := io.downCDRSampleIn(0).syncSerDat + upInSyncSerDat := io.upCDRSampleIn(0).syncSerDat + + io.downCDRSampleIn(1).serDat := false.B + io.upCDRSampleIn(1).serDat := false.B + io.downCDRSampleIn(2).serDat := false.B + io.upCDRSampleIn(2).serDat := false.B + } + + + } class MstSlvSwitch extends MstSlvSwitchBase diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala index db9567d..a25b868 100644 --- a/src/main/scala/backBoard/shin/ShinTop.scala +++ b/src/main/scala/backBoard/shin/ShinTop.scala @@ -14,22 +14,42 @@ class ShinTop extends Module with RequireAsyncReset{ val io: ShinTopIO = IO(new ShinTopIO) val mstSlvSwitch = Module(new MstSlvSwitch) - val downCDROut = Module(new CDROut) - val upCDROut = Module(new CDROut) - - val downCDRIn = Module(new MPCDRIn) - val upCDRIn = Module(new MPCDRIn) - downCDRIn.multiCLK := io.multiCLK - upCDRIn.multiCLK := io.multiCLK + { + val downCDRInSampleA = Module(new CDRInMultiSample) + val upCDRInSampleA = Module(new CDRInMultiSample) - downCDROut.io <> mstSlvSwitch.io.downCDROut - upCDROut.io <> mstSlvSwitch.io.upCDROut + downCDRInSampleA.multiCLK := io.multiCLK + upCDRInSampleA.multiCLK := io.multiCLK + + downCDRInSampleA.io <> mstSlvSwitch.io.downCDRSampleIn(0) + upCDRInSampleA.io <> mstSlvSwitch.io.upCDRSampleIn(0) + } + + { + val downCDRInSampleB = Module(new CDRInMultiSample) + val upCDRInSampleB = Module(new CDRInMultiSample) + + downCDRInSampleB.multiCLK := io.multiCLK + upCDRInSampleB.multiCLK := io.multiCLK + + downCDRInSampleB.io <> mstSlvSwitch.io.downCDRSampleIn(1) + upCDRInSampleB.io <> mstSlvSwitch.io.upCDRSampleIn(1) + } + + { + val downCDRInSampleC = Module(new CDRInMultiSample) + val upCDRInSampleC = Module(new CDRInMultiSample) + + downCDRInSampleC.multiCLK := io.multiCLK + upCDRInSampleC.multiCLK := io.multiCLK + + downCDRInSampleC.io <> mstSlvSwitch.io.downCDRSampleIn(2) + upCDRInSampleC.io <> mstSlvSwitch.io.upCDRSampleIn(2) + } - downCDRIn.io <> mstSlvSwitch.io.downCDRIn - upCDRIn.io <> mstSlvSwitch.io.upCDRIn io.viewAsSupertype(new TopBase_IO_Bundle) <> mstSlvSwitch.io.viewAsSupertype(new TopBase_IO_Bundle) diff --git a/src/test/scala/SimCDR.scala b/src/test/scala/SimCDR.scala index db2159c..6a3298c 100644 --- a/src/test/scala/SimCDR.scala +++ b/src/test/scala/SimCDR.scala @@ -20,7 +20,9 @@ class SimCDR extends Module with RequireAsyncReset{ - val cdrIn = Module(new MPCDRIn) + val cdrInAxis = Module(new CDRInAxis) + val cdrInSample = Module(new CDRInMultiSample) + val cdrOut = Module(new CDROut) val record = Module( new Queue(UInt(8.W), 256) ) @@ -52,11 +54,14 @@ class SimCDR extends Module with RequireAsyncReset{ cdrOut.io.flush := io.flush - cdrIn.clock := io.multiCLK(0).asClock - cdrIn.io.flush := io.flush - cdrIn.multiCLK := io.multiCLK + cdrInAxis.clock := io.multiCLK(0).asClock + cdrInSample.clock := io.multiCLK(0).asClock + cdrInAxis.io.flush := io.flush + cdrInSample.multiCLK := io.multiCLK + cdrInAxis.io.syncSerDat := cdrInSample.io.syncSerDat - cdrIn.io.serDat := cdrOut.io.serDat + + cdrInSample.io.serDat := cdrOut.io.serDat assert( ~(record.io.enq.valid & ~record.io.enq.ready), "Assert Failed, Warning, fifo overflow!\n" ) assert( ~(~record.io.deq.valid & record.io.deq.ready), "Assert Failed, Warning, fifo underflow!\n" ) @@ -73,11 +78,11 @@ class SimCDR extends Module with RequireAsyncReset{ record.io.enq.valid := cdrOut.io.axis.fire record.io.enq.bits := io.data - record.io.deq.ready := cdrIn.io.axis.fire - cdrIn.io.axis.ready := true.B + record.io.deq.ready := cdrInAxis.io.axis.fire + cdrInAxis.io.axis.ready := true.B - io.isFailed := cdrIn.io.axis.fire & (record.io.deq.bits =/= cdrIn.io.axis.bits.tdata) - io.isSuccess := cdrIn.io.axis.fire & cdrIn.io.axis.bits.tlast + io.isFailed := cdrInAxis.io.axis.fire & (record.io.deq.bits =/= cdrInAxis.io.axis.bits.tdata) + io.isSuccess := cdrInAxis.io.axis.fire & cdrInAxis.io.axis.bits.tlast @@ -87,14 +92,14 @@ class SimCDR extends Module with RequireAsyncReset{ when( isUsing8b10b ){ b8b10Encoder.io <> cdrOut.io.encode - b8b10Decoder.io <> cdrIn.io.decode + b8b10Decoder.io <> cdrInAxis.io.decode b4b5Encoder.io.isEnable := false.B b4b5Encoder.io.dataIn := 0.U b4b5Decoder.io.dataIn := 0.U } .otherwise{ b4b5Encoder.io <> cdrOut.io.encode - b4b5Decoder.io <> cdrIn.io.decode + b4b5Decoder.io <> cdrInAxis.io.decode b8b10Encoder.io.isEnable := false.B b8b10Encoder.io.dataIn := 0.U