拆分CDRIn为采样部分和axis部分；调整层次结构，仅将cdrInSample放在顶层；放置3组CDRInSample，使用寄存器选择

src/main/scala/backBoard/shin/ShinTop.scala

@@ -14,22 +14,42 @@ class ShinTop extends Module with RequireAsyncReset{
   val io: ShinTopIO = IO(new ShinTopIO)
 
   val mstSlvSwitch = Module(new MstSlvSwitch)
-  val downCDROut = Module(new CDROut)
-  val upCDROut   = Module(new CDROut)
-
-  val downCDRIn = Module(new MPCDRIn)
-  val upCDRIn  = Module(new MPCDRIn)
 
 
-  downCDRIn.multiCLK := io.multiCLK
-  upCDRIn.multiCLK   := io.multiCLK
 
+  {
+    val downCDRInSampleA = Module(new CDRInMultiSample)
+    val upCDRInSampleA  = Module(new CDRInMultiSample)
 
-  downCDROut.io <> mstSlvSwitch.io.downCDROut
-  upCDROut.io   <> mstSlvSwitch.io.upCDROut
+    downCDRInSampleA.multiCLK := io.multiCLK
+    upCDRInSampleA.multiCLK   := io.multiCLK
+
+    downCDRInSampleA.io  <> mstSlvSwitch.io.downCDRSampleIn(0)
+    upCDRInSampleA.io    <> mstSlvSwitch.io.upCDRSampleIn(0)  
+  }
+
+  {
+    val downCDRInSampleB = Module(new CDRInMultiSample)
+    val upCDRInSampleB  = Module(new CDRInMultiSample)
+
+    downCDRInSampleB.multiCLK := io.multiCLK
+    upCDRInSampleB.multiCLK   := io.multiCLK
+
+    downCDRInSampleB.io  <> mstSlvSwitch.io.downCDRSampleIn(1)
+    upCDRInSampleB.io    <> mstSlvSwitch.io.upCDRSampleIn(1)
+  }
+
+  {
+    val downCDRInSampleC = Module(new CDRInMultiSample)
+    val upCDRInSampleC  = Module(new CDRInMultiSample)
+
+    downCDRInSampleC.multiCLK := io.multiCLK
+    upCDRInSampleC.multiCLK   := io.multiCLK
+
+    downCDRInSampleC.io  <> mstSlvSwitch.io.downCDRSampleIn(2)
+    upCDRInSampleC.io    <> mstSlvSwitch.io.upCDRSampleIn(2)  
+  }
 
-  downCDRIn.io  <> mstSlvSwitch.io.downCDRIn
-  upCDRIn.io    <> mstSlvSwitch.io.upCDRIn
 
 
   io.viewAsSupertype(new TopBase_IO_Bundle) <> mstSlvSwitch.io.viewAsSupertype(new TopBase_IO_Bundle)