拆分CDRIn为采样部分和axis部分；调整层次结构，仅将cdrInSample放在顶层；放置3组CDRInSample，使用寄存器选择

src/main/scala/backBoard/ebus/CDRIn.scala

@@ -5,34 +5,17 @@ import chisel3.util._
 
 
 
-
-
-
-//work in 100MHZ
-class CDRInIO extends Bundle{
-  val axis = Decoupled(new AXIS_Bundle(8))
-  val decode = Flipped(new Decode_Bundle)
+class CDRInSampleIO extends Bundle{
   val serDat = Input(Bool())
-  val flush = Input(Bool())
+  val syncSerDat = Output(Bool())
 }
 
 
-
-
-abstract class CDRInBase extends Module with RequireAsyncReset{
-  val io: CDRInIO = IO(new CDRInIO)
-  io.decode.dataIn := 0.U
-
-  val syncSerDat = Wire(Bool())
-}
-
-
-trait CDRInMultiSample{ this: CDRInBase =>
-  
+class CDRInMultiSample extends Module with RequireAsyncReset{
+  val io: CDRInSampleIO = IO(new CDRInSampleIO)
   val clkNum: Int = 16
   require( clkNum == 16 )
 
-
   //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
   val multiCLK = IO(Input(Vec(clkNum, Bool())))
 
@@ -196,14 +179,22 @@ trait CDRInMultiSample{ this: CDRInBase =>
     )
 
 
-  syncSerDat := asyncSerDat
+  io.syncSerDat := asyncSerDat
 
 }
 
+class CDRInAxisIO extends Bundle{
+  val axis = Decoupled(new AXIS_Bundle(8))
+  val decode = Flipped(new Decode_Bundle)
+  val syncSerDat = Input(Bool())
 
+  val flush = Input(Bool())
+}
 
-trait CDRInAxis{ this: CDRInBase =>
+class CDRInAxis extends Module with RequireAsyncReset{
+  val io: CDRInAxisIO = IO(new CDRInAxisIO)
 
+  io.decode.dataIn := 0.U
   def HeaderByte: Int = 4
 
   val ETH_PRE = "h68".U(8.W)
@@ -224,7 +215,7 @@ trait CDRInAxis{ this: CDRInBase =>
   when( io.flush ){
     checkSFD := 0.U
   } .otherwise{
-    checkSFD := Cat( checkSFD(8,0), syncSerDat )
+    checkSFD := Cat( checkSFD(8,0), io.syncSerDat )
   }
 
   io.decode.dataIn := checkSFD(9,0)
@@ -310,7 +301,5 @@ trait CDRInAxis{ this: CDRInBase =>
 
 }
 
-class MPCDRIn extends CDRInBase 
-with CDRInAxis
-with CDRInMultiSample
+