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Rx的req resp跨时钟架构

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RuigeLee
2023-10-23 22:58:36 +08:00
parent bf66bae475
commit faa46be8ef
3 changed files with 55 additions and 27 deletions
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29
src/main/scala/Switch/mac/MAC.scala
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@@ -800,19 +800,28 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
val RxAbortSync = ShiftRegister( macTileLinkRx.io.RxAbortLatched, 2, false.B, true.B )
wishbone.io.RxAbortSync := RxAbortSync
val ShiftEndedSync = ShiftRegister( macTileLinkRx.io.ShiftEnded_rck, 2, false.B, true.B )
wishbone.io.ShiftEndedSync := ShiftEndedSync
// val ShiftEndedSync = ShiftRegister( macTileLinkRx.io.ShiftEnded_rck, 2, false.B, true.B )
// wishbone.io.ShiftEndedSync := ShiftEndedSync
val req_ToAsync = Wire(new AsyncBundle(UInt(8.W)))
val req_ToAsync = Wire(new AsyncBundle(new RxFifo_Stream_Bundle))
val resp_ToAsync = Wire(new AsyncBundle(Bool()))
val fateRxRespPort = Wire( Flipped(Decoupled(Bool())) )
fateRxRespPort.ready := true.B
wishbone.io.syncToBuf <> FromAsyncBundle( req_ToAsync )
wishbone.io.rxReq <> FromAsyncBundle( req_ToAsync )
resp_ToAsync <> ToAsyncBundle( wishbone.io.rxResp )
withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset) {
req_ToAsync <> ToAsyncBundle( macTileLinkRx.io.asyncToBuf )
withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset) {
req_ToAsync <> ToAsyncBundle( macTileLinkRx.io.rxReq )
fateRxRespPort <> FromAsyncBundle( resp_ToAsync )
}
wishbone.io.LatchedRxLength_rxclk := macTileLinkRx.io.LatchedRxLength
wishbone.io.RxStatusInLatched_rxclk := macTileLinkRx.io.RxStatusInLatched
@@ -824,10 +833,10 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
Busy_IRQ := Busy_IRQ_sync & ~RegNext(Busy_IRQ_sync, false.B)
withClockAndReset( io.mii.mrx_clk_pad_i.asClock, io.asyncReset ) {
val ShiftEndedSyncb = ShiftRegister( ShiftEndedSync, 3, false.B, true.B) //async 3 cycle for protect wishbone.io.syncToBuf.valid
// val ShiftEndedSyncb = ShiftRegister( ShiftEndedSync, 3, false.B, true.B) //async 3 cycle for protect wishbone.io.syncToBuf.valid
println("Warning, No protect in ShiftEndedSyncb?!")
RxStatusWriteLatchedSync := ShiftEndedSyncb
macTileLinkRx.io.ShiftEndedSyncb := ShiftEndedSyncb
RxStatusWriteLatchedSync := fateRxRespPort.fire
// macTileLinkRx.io.ShiftEndedSyncb := fateRxRespPort.fire
macTileLinkRx.io.RxAbortSyncb := ShiftRegister( RxAbortSync, 2, false.B, true.B )
macTileLinkRx.io.Busy_IRQ_syncb := ShiftRegister( Busy_IRQ_sync, 2, false.B, true.B )