diff --git a/src/main/scala/Switch/mac/MAC.scala b/src/main/scala/Switch/mac/MAC.scala
index fe002ec..4c541ef 100644
--- a/src/main/scala/Switch/mac/MAC.scala
+++ b/src/main/scala/Switch/mac/MAC.scala
@@ -800,19 +800,28 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
   val RxAbortSync           = ShiftRegister( macTileLinkRx.io.RxAbortLatched, 2, false.B, true.B )
   wishbone.io.RxAbortSync  := RxAbortSync
 
-  val ShiftEndedSync = ShiftRegister( macTileLinkRx.io.ShiftEnded_rck, 2, false.B, true.B )
-  wishbone.io.ShiftEndedSync := ShiftEndedSync
+  // val ShiftEndedSync = ShiftRegister( macTileLinkRx.io.ShiftEnded_rck, 2, false.B, true.B )
+  // wishbone.io.ShiftEndedSync := ShiftEndedSync
   
 
-  val req_ToAsync = Wire(new AsyncBundle(UInt(8.W)))
-
+  val req_ToAsync = Wire(new AsyncBundle(new RxFifo_Stream_Bundle))
+  val resp_ToAsync = Wire(new AsyncBundle(Bool()))
+  val fateRxRespPort = Wire( Flipped(Decoupled(Bool())) )
+  fateRxRespPort.ready := true.B
  
-  wishbone.io.syncToBuf <> FromAsyncBundle( req_ToAsync )
+  wishbone.io.rxReq <> FromAsyncBundle( req_ToAsync )
+  resp_ToAsync <> ToAsyncBundle( wishbone.io.rxResp )
 
-  withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset) {   
-    req_ToAsync <> ToAsyncBundle( macTileLinkRx.io.asyncToBuf )
+  withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset) {  
+    req_ToAsync <> ToAsyncBundle( macTileLinkRx.io.rxReq )
+    fateRxRespPort <> FromAsyncBundle( resp_ToAsync )  
   }
 
+    
+    
+
+
+
 
   wishbone.io.LatchedRxLength_rxclk   := macTileLinkRx.io.LatchedRxLength
   wishbone.io.RxStatusInLatched_rxclk := macTileLinkRx.io.RxStatusInLatched
@@ -824,10 +833,10 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
   Busy_IRQ := Busy_IRQ_sync & ~RegNext(Busy_IRQ_sync, false.B)
 
   withClockAndReset( io.mii.mrx_clk_pad_i.asClock, io.asyncReset ) {
-    val ShiftEndedSyncb = ShiftRegister( ShiftEndedSync, 3, false.B, true.B) //async 3 cycle for protect wishbone.io.syncToBuf.valid
+    // val ShiftEndedSyncb = ShiftRegister( ShiftEndedSync, 3, false.B, true.B) //async 3 cycle for protect wishbone.io.syncToBuf.valid
     println("Warning, No protect in ShiftEndedSyncb?!")
-    RxStatusWriteLatchedSync         := ShiftEndedSyncb 
-    macTileLinkRx.io.ShiftEndedSyncb := ShiftEndedSyncb 
+    RxStatusWriteLatchedSync         := fateRxRespPort.fire
+    // macTileLinkRx.io.ShiftEndedSyncb := fateRxRespPort.fire
     macTileLinkRx.io.RxAbortSyncb    := ShiftRegister( RxAbortSync,    2, false.B, true.B )
     macTileLinkRx.io.Busy_IRQ_syncb  := ShiftRegister( Busy_IRQ_sync,  2, false.B, true.B )
 
diff --git a/src/main/scala/Switch/mac/MacTileLinkRx.scala b/src/main/scala/Switch/mac/MacTileLinkRx.scala
index d0e3b4b..501952b 100644
--- a/src/main/scala/Switch/mac/MacTileLinkRx.scala
+++ b/src/main/scala/Switch/mac/MacTileLinkRx.scala
@@ -4,22 +4,28 @@ import chisel3._
 import chisel3.util._
 
 
+class RxFifo_Stream_Bundle extends Bundle{
+  val data = UInt(8.W)
+  val isLast = Bool()
+}
+
+
 
 class MacTileLinkRxIO extends Bundle{
     // val RxDataLatched2 = Output(UInt(8.W))
     // val WriteRxDataToFifo = Output(Bool())
 
-  val asyncToBuf = Decoupled(UInt(8.W))
+  val rxReq = Decoupled(new RxFifo_Stream_Bundle)
 
   val RxAbortLatched = Output(Bool())
   val LatchedRxLength = Output(UInt(16.W))
   val RxStatusInLatched = Output( UInt(9.W) )
-  val ShiftEnded_rck = Output(Bool())
+  // val ShiftEnded_rck = Output(Bool())
 
   val RxLength = Input(UInt(16.W))
   val LoadRxStatus = Input(Bool())
       val RxStatusIn = Input(UInt(9.W))
-  val ShiftEndedSyncb = Input(Bool())
+  // val ShiftEndedSyncb = Input(Bool())
   val RxAbortSyncb = Input(Bool())
   // val WriteRxDataToFifoSyncb = Input(Bool())
 
@@ -45,7 +51,7 @@ class MacTileLinkRx extends Module with RequireAsyncReset{
   val LatchedRxLength = RegEnable(io.RxLength, 0.U(16.W), io.LoadRxStatus); io.LatchedRxLength   := LatchedRxLength
   val RxStatusInLatched = RegEnable(io.RxStatusIn, 0.U(9.W), io.LoadRxStatus); io.RxStatusInLatched := RxStatusInLatched
 
-  val ShiftEnded_rck = RegInit(false.B); io.ShiftEnded_rck := ShiftEnded_rck
+  // val ShiftEnded_rck = RegInit(false.B); io.ShiftEnded_rck := ShiftEnded_rck
   val RxEnableWindow = RegInit(false.B)
   
   val Busy_IRQ_rck = RegInit(false.B); io.Busy_IRQ_rck := Busy_IRQ_rck
@@ -64,12 +70,12 @@ class MacTileLinkRx extends Module with RequireAsyncReset{
         //   WriteRxDataToFifo := false.B
         // }
 
-    // Generation of the end-of-frame signal
-    when(SetWriteRxDataToFifo & ~io.RxAbort & io.RxEndFrm){
-      ShiftEnded_rck := true.B
-    } .elsewhen(io.RxAbort | io.ShiftEndedSyncb & RegNext(io.ShiftEndedSyncb, false.B) ){
-      ShiftEnded_rck := false.B
-    }
+    // // Generation of the end-of-frame signal
+    // when(SetWriteRxDataToFifo & ~io.RxAbort & io.RxEndFrm){
+    //   ShiftEnded_rck := true.B
+    // } .elsewhen(io.RxAbort | io.ShiftEndedSyncb & RegNext(io.ShiftEndedSyncb, false.B) ){
+    //   ShiftEnded_rck := false.B
+    // }
 
     // Generation of the end-of-frame signal
     when(io.RxStartFrm){
@@ -92,12 +98,13 @@ class MacTileLinkRx extends Module with RequireAsyncReset{
     }
 
 
-  val rxFifo = Module(new Queue(UInt(8.W), 4))
+  val rxFifo = Module(new Queue(new RxFifo_Stream_Bundle, 4))
   rxFifo.io.enq.valid := SetWriteRxDataToFifo & ~io.RxAbort
-  rxFifo.io.enq.bits  := io.RxData
+  rxFifo.io.enq.bits.data   := io.RxData
+  rxFifo.io.enq.bits.isLast := io.RxEndFrm
   assert( ~(rxFifo.io.enq.valid & ~rxFifo.io.enq.ready) )
 
-  io.asyncToBuf <> rxFifo.io.deq
+  io.rxReq <> rxFifo.io.deq
 }
 
 
diff --git a/src/main/scala/Switch/mac/MacTilelink.scala b/src/main/scala/Switch/mac/MacTilelink.scala
index 26f5ae7..db7e172 100644
--- a/src/main/scala/Switch/mac/MacTilelink.scala
+++ b/src/main/scala/Switch/mac/MacTilelink.scala
@@ -21,13 +21,14 @@ abstract class MacTileLinkBase() extends Module{
 
     val r_RxEn    = Input(Bool())         // Receive enable
 
-    val syncToBuf = Flipped(Decoupled(UInt(8.W)))
+    val rxReq = Flipped(Decoupled(new RxFifo_Stream_Bundle))
+    val rxResp = Decoupled(new Bool())
       // val RxDataLatched2_rxclk  = Input(UInt(8.W))
       // val WriteRxDataToFifoSync = Input(Bool())
     val RxAbortSync           = Input(Bool())
     val LatchedRxLength_rxclk = Input(UInt(16.W))
     val RxStatusInLatched_rxclk = Input(UInt(9.W))
-    val ShiftEndedSync = Input(Bool())
+    // val ShiftEndedSync = Input(Bool())
     val RxReady = Output(Bool())
 
 
@@ -69,7 +70,7 @@ abstract class MacTileLinkBase() extends Module{
 
 
 
-  val ShiftEndedSyncPluse         = io.ShiftEndedSync & io.syncToBuf.valid          & ~RegNext(io.ShiftEndedSync & io.syncToBuf.valid, false.B)
+  val ShiftEndedSyncPluse         = io.rxReq.bits.isLast & io.rxReq.fire
   val RxAbortPluse                = io.RxAbortSync             & ~RegNext(io.RxAbortSync, false.B)
   // val WriteRxDataToFifoSyncPluse  = io.WriteRxDataToFifoSync   & ~RegNext(io.WriteRxDataToFifoSync, false.B)
 
@@ -98,7 +99,18 @@ abstract class MacTileLinkBase() extends Module{
   }
 
 
-  io.rxEnq.data <> io.syncToBuf
+  io.rxEnq.data.bits  := io.rxReq.bits.data
+  io.rxEnq.data.valid := io.rxReq.valid
+  io.rxReq.ready      := io.rxEnq.data.ready
+
+  val rxRespValid = RegInit(false.B)
+  when( io.rxResp.fire ){
+    rxRespValid := false.B
+  } .elsewhen( ShiftEndedSyncPluse ){
+    rxRespValid := true.B
+  }
+  io.rxResp.valid := rxRespValid
+  io.rxResp.bits  := DontCare
 
   assert( ~(io.rxEnq.data.valid & ~io.rxEnq.data.ready), "Assert Failed, rx overrun!" )