spi写pll寄存器信号拉到顶层

src/main/scala/backBoard/shin/MstSlvSwitch.scala

@@ -32,6 +32,7 @@ class TopBase_IO_Bundle extends Bundle{
   val bias   = Output(UInt(2.W))
 
   val spiSel  = Output(UInt(2.W))
+  val isPllCfg = Output(Bool())
 }
 
 
@@ -91,7 +92,8 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{
   io.refTop    := interface.io.cReg.refTop
   io.bias      := interface.io.cReg.bias
 
-  io.spiSel  := interface.io.cReg.spiSel
+  io.spiSel   := interface.io.cReg.spiSel
+  io.isPllCfg := interface.io.isPllCfg
 
   val sram = Seq(
     for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },