From fa3ba57f3257f30b413c2cb531f6b4cde161b278 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Wed, 27 Aug 2025 15:20:43 +0800 Subject: [PATCH] =?UTF-8?q?spi=E5=86=99pll=E5=AF=84=E5=AD=98=E5=99=A8?= =?UTF-8?q?=E4=BF=A1=E5=8F=B7=E6=8B=89=E5=88=B0=E9=A1=B6=E5=B1=82?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 13 ++++++++----- src/main/scala/backBoard/shin/MstSlvSwitch.scala | 4 +++- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index 9c70cb0..0270c66 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -210,6 +210,7 @@ class InterfaceIO extends Bundle{ val hwSerial = Input(UInt(48.W)) val uniCode = Input(UInt(64.W)) + val isPllCfg = Output(Bool()) } @@ -1312,11 +1313,13 @@ trait InterfaceAnalog{ this: InterfaceBase => ) - cReg.anamuxSel := RegEnable( dataw, "h0".U(8.W), isEnW & addrw === "h50".U ) - cReg.ldo2p5 := RegEnable( dataw, "h87".U(8.W), isEnW & addrw === "h51".U ) - cReg.ldo1p1 := RegEnable( dataw, "h87".U(8.W), isEnW & addrw === "h52".U ) - cReg.refTop := RegEnable( dataw, "h0".U(8.W), isEnW & addrw === "h53".U ) - cReg.bias := RegEnable( dataw, "h0".U(8.W), isEnW & addrw === "h54".U ) + cReg.anamuxSel := RegEnable( dataw, "h0".U(8.W), isEnW & addrw === "h50".U ) + cReg.ldo2p5 := RegEnable( dataw, "h87".U(8.W), isEnW & addrw === "h51".U ) + cReg.ldo1p1 := RegEnable( dataw, "h87".U(8.W), isEnW & addrw === "h52".U ) + cReg.refTop := RegEnable( dataw, "h0".U(8.W), isEnW & addrw === "h53".U ) + cReg.bias := RegEnable( dataw, "h0".U(8.W), isEnW & addrw === "h54".U ) + + io.isPllCfg := isEnW & addrw === "h45".U } trait InterfaceStat{ this: InterfaceBase => diff --git a/src/main/scala/backBoard/shin/MstSlvSwitch.scala b/src/main/scala/backBoard/shin/MstSlvSwitch.scala index 8bdfac4..07eeda8 100644 --- a/src/main/scala/backBoard/shin/MstSlvSwitch.scala +++ b/src/main/scala/backBoard/shin/MstSlvSwitch.scala @@ -32,6 +32,7 @@ class TopBase_IO_Bundle extends Bundle{ val bias = Output(UInt(2.W)) val spiSel = Output(UInt(2.W)) + val isPllCfg = Output(Bool()) } @@ -91,7 +92,8 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{ io.refTop := interface.io.cReg.refTop io.bias := interface.io.cReg.bias - io.spiSel := interface.io.cReg.spiSel + io.spiSel := interface.io.cReg.spiSel + io.isPllCfg := interface.io.isPllCfg val sram = Seq( for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },