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spi写pll寄存器信号拉到顶层

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This commit is contained in:
Ruige Lee
2025-08-27 15:20:43 +08:00
parent dd71c557b7
commit fa3ba57f32
2 changed files with 11 additions and 6 deletions
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13
src/main/scala/backBoard/shin/Interface.scala
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@@ -210,6 +210,7 @@ class InterfaceIO extends Bundle{
val hwSerial = Input(UInt(48.W))
val uniCode = Input(UInt(64.W))
val isPllCfg = Output(Bool())
}
@@ -1312,11 +1313,13 @@ trait InterfaceAnalog{ this: InterfaceBase =>
)
cReg.anamuxSel := RegEnable( dataw, "h0".U(8.W), isEnW & addrw === "h50".U )
cReg.ldo2p5 := RegEnable( dataw, "h87".U(8.W), isEnW & addrw === "h51".U )
cReg.ldo1p1 := RegEnable( dataw, "h87".U(8.W), isEnW & addrw === "h52".U )
cReg.refTop := RegEnable( dataw, "h0".U(8.W), isEnW & addrw === "h53".U )
cReg.bias := RegEnable( dataw, "h0".U(8.W), isEnW & addrw === "h54".U )
cReg.anamuxSel := RegEnable( dataw, "h0".U(8.W), isEnW & addrw === "h50".U )
cReg.ldo2p5 := RegEnable( dataw, "h87".U(8.W), isEnW & addrw === "h51".U )
cReg.ldo1p1 := RegEnable( dataw, "h87".U(8.W), isEnW & addrw === "h52".U )
cReg.refTop := RegEnable( dataw, "h0".U(8.W), isEnW & addrw === "h53".U )
cReg.bias := RegEnable( dataw, "h0".U(8.W), isEnW & addrw === "h54".U )
io.isPllCfg := isEnW & addrw === "h45".U
}
trait InterfaceStat{ this: InterfaceBase =>