从站初始化逻辑写完，准备编译开始第一轮测试
This commit is contained in:
RuigeLee
@@ -3,6 +3,27 @@ package BACK
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import chisel3._
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import chisel3.util._
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class ShinSlvIO_Bundle extends Bundle{
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val isOnline = Output(Bool())
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val isLast = Input(Bool())
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val DCIn = Input(Bool())
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val downSer = new Bundle{
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val out = Output(Bool())
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val in = Input(Bool())
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}
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val upSer = new Bundle{
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val out = Output(Bool())
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val in = Input(Bool())
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}
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val overCLK = Input(Bool())
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}
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abstract class ShinSlvPhyBase extends Module{
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val downStreamCdrOut = Module(new CDROut)
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@@ -11,6 +32,17 @@ abstract class ShinSlvPhyBase extends Module{
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val upStreamCdrOut = Module(new CDROut)
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val upStreamCdrIn = Module(new CDRIn )
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io.downSer.out := downStreamCdrOut.io.serDat
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downStreamCdrIn.io.serDat := io.downSer.in
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downStreamCdrIn.io.overCLK := io.overCLK
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io.upSer.out := upStreamCdrOut.io.serDat
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upStreamCdrIn.io.serDat := io.upSer.in
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upStreamCdrIn.io.overCLK := io.overCLK
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io.isOnline := true.B
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val downRegTemp = Reg(Vec( 32, UInt(8.W) ))
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val upReg = WireDefault(VecInit((0 until 32).map{i => 0.U(8.W)}))
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@@ -24,9 +56,11 @@ abstract class ShinSlvPhyBase extends Module{
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val maxLocalByte = OpInitByte max OpBoardCastByte max OpUniCastByte
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val isLastDevice: Bool
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}
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trait ShinSlvPhyDownStream{ this: ShinSlvPhyBase =>
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trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase =>
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val DownRecvStateIdle = 0.U
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val DownRecvStateOHead = 1.U
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@@ -35,10 +69,6 @@ trait ShinSlvPhyDownStream{ this: ShinSlvPhyBase =>
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val DownRecvStateCRC = 4.U
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val DownSendStateIdle = 0.U
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val DownSendStateNHead = 1.U
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val DownSendStateFData = 2.U
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val downOldHead = Reg( new Header_Info_Bundle )
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val downNewHead = Reg( new Header_Info_Bundle )
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@@ -48,9 +78,9 @@ trait ShinSlvPhyDownStream{ this: ShinSlvPhyBase =>
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val downRecvStateCurr = RegNext( downRecvSteteNext, 0.U )
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val downRecvCnt = Reg(UInt(10.W))
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val downSendCnt = Reg(UInt(10.W))
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val selfDataByte = Mux1H(Seq(
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val downLocalDataByte = Mux1H(Seq(
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(downOldHead.operator === 0.U) -> OpInitByte,
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(downOldHead.operator === 1.U) -> OpBoardCastByte,
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(downOldHead.operator === 2.U) -> OpUniCastByte,
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@@ -58,14 +88,14 @@ trait ShinSlvPhyDownStream{ this: ShinSlvPhyBase =>
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val isDownStreamError = RegInit( false.B )
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val forwardDataByte = downNewHead.length
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val downForwardDataByte = downNewHead.length
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downRecvSteteNext := Mux1H(Seq(
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(downRecvStateCurr === DownRecvStateIdle ) -> Mux( downStreamCdrIn.io.axis.valid, DownRecvStateOHead, DownRecvStateIdle ),
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(downRecvStateCurr === DownRecvStateOHead) -> Mux( downStreamCdrIn.io.axis.fire, Mux( ~downStreamCdrIn.io.axis.bits.tlast, Mux(downRecvCnt === ((headByte)-1).U, DownRecvStateSData, DownRecvStateOHead), DownRecvStateIdle ), DownRecvStateOHead),
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(downRecvStateCurr === DownRecvStateSData) -> Mux( downStreamCdrIn.io.axis.fire, Mux( ~downStreamCdrIn.io.axis.bits.tlast, Mux(downRecvCnt === (selfDataByte -1.U), DownRecvStateFData, DownRecvStateSData), DownRecvStateIdle ), DownRecvStateSData),
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(downRecvStateCurr === DownRecvStateFData) -> Mux( downStreamCdrIn.io.axis.fire, Mux( ~downStreamCdrIn.io.axis.bits.tlast, Mux(downRecvCnt === (forwardDataByte -1.U) , DownRecvStateCRC, DownRecvStateFData), DownRecvStateIdle ), DownRecvStateFData),
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(downRecvStateCurr === DownRecvStateSData) -> Mux( downStreamCdrIn.io.axis.fire, Mux( ~downStreamCdrIn.io.axis.bits.tlast, Mux(downRecvCnt === (downLocalDataByte -1.U), Mux( downRecvCnt === (downOldHead.length - 1.U), DownRecvStateCRC, DownRecvStateFData ), DownRecvStateSData), DownRecvStateIdle ), DownRecvStateSData),
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(downRecvStateCurr === DownRecvStateFData) -> Mux( downStreamCdrIn.io.axis.fire, Mux( ~downStreamCdrIn.io.axis.bits.tlast, Mux(downRecvCnt === (downForwardDataByte -1.U) , DownRecvStateCRC, DownRecvStateFData), DownRecvStateIdle ), DownRecvStateFData),
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(downRecvStateCurr === DownRecvStateCRC ) -> Mux( downStreamCdrIn.io.axis.fire & downStreamCdrIn.io.axis.bits.tlast, DownRecvStateIdle, DownRecvStateCRC ),
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))
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@@ -83,9 +113,9 @@ trait ShinSlvPhyDownStream{ this: ShinSlvPhyBase =>
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//---------------
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val isNewHeadCreated = downRecvStateCurr === DownRecvStateSData & downRecvSteteNext === DownRecvStateFData //新头是由老头产生，担忧会欠拍
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when( isNewHeadCreated ){
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downNewHead.length := Mux( downOldHead.length >= selfDataByte, downOldHead.length - selfDataByte, 0.U )
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val isDownNewHeadCreated = downRecvStateCurr === DownRecvStateSData & downRecvSteteNext === DownRecvStateFData //新头是由老头产生，担忧会欠拍
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when( isDownNewHeadCreated ){
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downNewHead.length := Mux( downOldHead.length >= downLocalDataByte, downOldHead.length - downLocalDataByte, 0.U )
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downNewHead.operator := downOldHead.operator
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downNewHead.param := downOldHead.param
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}
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@@ -97,34 +127,39 @@ trait ShinSlvPhyDownStream{ this: ShinSlvPhyBase =>
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//---------------
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downStreamFifo.io.enq.valid :=
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downRecvStateCurr === DownRecvStateFData & downStreamCdrIn.io.axis.valid
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downRecvStateCurr === DownRecvStateFData & downStreamCdrIn.io.axis.fire & ~isLastDevice
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downStreamFifo.io.enq.bits.tdata := downStreamCdrIn.io.axis.bits.tdata
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downStreamFifo.io.enq.bits.tuser := downStreamCdrIn.io.axis.bits.tuser
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downStreamFifo.io.enq.bits.tlast := downRecvCnt === (forwardDataByte -1.U) | downStreamCdrIn.io.axis.bits.tlast
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downStreamFifo.io.enq.bits.tlast := downRecvCnt === (downForwardDataByte -1.U) | downStreamCdrIn.io.axis.bits.tlast
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downStreamCdrIn.io.axis.ready :=
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(downRecvStateCurr === DownRecvStateOHead) |
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(downRecvStateCurr === DownRecvStateSData) |
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(downRecvStateCurr === DownRecvStateFData) |
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((downRecvStateCurr === DownRecvStateFData) & downStreamFifo.io.enq.ready) |
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(downRecvStateCurr === DownRecvStateCRC )
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when( downRecvStateCurr === DownRecvStateIdle & downRecvSteteNext === DownRecvStateOHead){
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isDownStreamError := false.B
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} .elsewhen( downStreamFifo.io.enq.fire & downStreamFifo.io.enq.bits.tuser ){
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isDownStreamError := true.B
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printf("Warning, Wrong Package Received, That could not happened!\n")
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} .elsewhen( downRecvStateCurr === DownRecvStateOHead & downRecvSteteNext === DownRecvStateOHead ){
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printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
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} .elsewhen( downRecvStateCurr === DownRecvStateOHead & downRecvSteteNext === DownRecvStateIdle ){
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isDownStreamError := true.B
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printf("Warning, Wrong Package Received, That could not happened!\n")
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} .elsewhen( downRecvStateCurr === DownRecvStateSHead & downRecvSteteNext === DownRecvStateOHead ){
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printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
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} .elsewhen( downRecvStateCurr === DownRecvStateSHead & downRecvSteteNext === DownRecvStateIdle ){
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isDownStreamError := true.B
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printf("Warning, Wrong Package Received, That could not happened!\n")
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} .elsewhen( downRecvStateCurr === DownRecvStateFHead & downRecvSteteNext === DownRecvStateOHead ){
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printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
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} .elsewhen( downRecvStateCurr === DownRecvStateFHead & downRecvSteteNext === DownRecvStateIdle ){
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isDownStreamError := true.B
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printf("Warning, Wrong Package Received, That could not happened!\n")
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printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
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} .elsewhen( downRecvStateCurr === DownRecvStateCRC & (downRecvCnt > 3.U | (downStreamCdrIn.io.axis.fire & downStreamCdrIn.io.axis.bits.tlast & downRecvCnt < 3.U)) ){
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isDownStreamError := true.B
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printf("Warning, Wrong Package Received, That could not happened!\n")
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printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
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} .elsewhen( isDownNewHeadCreated & downOldHead.length < downLocalDataByte ){ //本包的负载不能满足本级数据需求，传输错误
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isDownStreamError := true.B
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printf("Warning, Wrong Package Received in DownStream, That could not happened!\n")
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} .elsewhen( isLastDevice & downOldHead.length =/= downLocalDataByte ){
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printf("Warning, Wrong Package Received in DownStream, SoftWare Check!\n")
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}
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@@ -134,14 +169,23 @@ trait ShinSlvPhyDownStream{ this: ShinSlvPhyBase =>
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}
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trait ShinSlvPhyDownStreamSend{ this: ShinSlvPhyBase =>
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val DownSendStateIdle = 0.U
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val DownSendStateNHead = 1.U
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val DownSendStateFData = 2.U
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val downSendCnt = Reg(UInt(10.W))
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val downSendSteteNext = Wire( UInt(3.W) )
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val downSendStateCurr = RegNext( downSendSteteNext, 0.U )
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downSendSteteNext := Mux1H(Seq(
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( downSendStateCurr === DownSendStateIdle ) -> Mux( isNewHeadCreated, DownSendStateNHead, DownSendStateIdle ),
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( downSendStateCurr === DownSendStateIdle ) -> Mux( isDownNewHeadCreated & ~isLastDevice, DownSendStateNHead, DownSendStateIdle ),
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( downSendStateCurr === DownSendStateNHead ) -> Mux( downSendCnt === ((headByte)-1).U & downStreamCdrOut.io.axis.fire, DownSendStateFData, DownSendStateNHead ),
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( downSendStateCurr === DownSendStateFData ) -> Mux( downSendCnt === (forwardDataByte -1.U) & downStreamCdrOut.io.axis.fire, DownSendStateIdle, DownSendStateFData),
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( downSendStateCurr === DownSendStateFData ) -> Mux( downSendCnt === (downForwardDataByte -1.U) & downStreamCdrOut.io.axis.fire, DownSendStateIdle, DownSendStateFData),
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))
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when( downSendStateCurr =/= downSendSteteNext ){
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@@ -169,21 +213,21 @@ trait ShinSlvPhyDownStream{ this: ShinSlvPhyBase =>
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downSendStateCurr === DownSendStateFData & downStreamCdrOut.io.axis.ready
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assert( ~(downStreamCdrIn.io.axis.valid & ~downStreamCdrIn.io.axis.ready) )
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}
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abstract ShinSlvPhyDownStream extends ShinSlvPhyBase
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with ShinSlvPhyDownStreamRecv
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with ShinSlvPhyDownStreamSend{
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}
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trait ShinSlvPhyUpStream{ this: ShinSlvPhyBase =>
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trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream =>
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val UpRecvStateIdle = 0.U
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val UpRecvStateOHead = 1.U
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val UpRecvStateFData = 2.U
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val UpRecvStateCRC = 3.U
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val UpSendStateIdle = 0.U
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val UpSendStateNHead = 1.U
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val UpSendStateSHead = 2.U
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val UpSendStateFData = 3.U
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val upOldHead = Reg( new Header_Info_Bundle )
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val upNewHead = Reg( new Header_Info_Bundle )
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@@ -210,119 +254,155 @@ trait ShinSlvPhyUpStream{ this: ShinSlvPhyBase =>
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val isLastDownStreamEnd = ( isLastDevice & (downRecvStateCurr === DownRecvStateCRC & downRecvStateNext === DownRecvStateIdle))
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//---------------
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when( (upRecvStateCurr === UpRecvStateOHead & upStreamCdrIn.io.axis.fire) ){
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upOldHead := Cat( upOldHead.asUInt.tail(8), upStreamCdrIn.io.axis.tdata ).asTypeOf(Header_Info_Bundle)
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} .elsewhen( isLastDownStreamEnd ){
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upOldHead.operator := downOldHead.operator
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upOldHead.length := 0.U
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upOldHead.param := downOldHead.param
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}
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//---------------
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val upLocalDataByte = Mux1H(Seq(
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(upOldHead.operator === 0.U) -> OpInitByte,
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(upOldHead.operator === 1.U) -> OpBoardCastByte,
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(upOldHead.operator === 2.U) -> OpUniCastByte,
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))
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val isUpNewHeadCreated =
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RegNext(upRecvStateCurr === UpRecvStateOHead & upRecvSteteNext === UpRecvStateFData, false.B) | //补一拍
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isLastDownStreamEnd
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when( isUpNewHeadCreated ){
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upNewHead.length := upOldHead.length + upLocalDataByte
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upNewHead.operator := upOldHead.operator
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upNewHead.param := upOldHead.param
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}
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val upForwardDataByte = upNewHead.length
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//---------------
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upStreamFifo.io.enq.valid :=
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upRecvStateCurr === UpRecvStateFData & upStreamCdrIn.io.axis.fire
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upStreamFifo.io.enq.bits.tdata := upStreamCdrIn.io.axis.bits.tdata
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upStreamFifo.io.enq.bits.tuser := upStreamCdrIn.io.axis.bits.tuser
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upStreamFifo.io.enq.bits.tlast := upRecvCnt === (upForwardDataByte -1.U) | upStreamCdrIn.io.axis.bits.tlast
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upStreamCdrIn.io.axis.ready :=
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(upRecvStateCurr === UpRecvStateOHead) |
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((upRecvStateCurr === UpRecvStateFData) & upStreamFifo.io.enq.ready) |
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(upRecvStateCurr === UpRecvStateCRC )
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val isUpStreamError = RegInit( false.B )
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when( (upRecvStateCurr === UpRecvStateIdle & upRecvSteteNext === UpRecvStateOHead) | isLastDownStreamEnd ){
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isUpStreamError := false.B
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} .elsewhen( upStreamFifo.io.enq.fire & upStreamFifo.io.enq.bits.tuser ){
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isUpStreamError := true.B
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printf("Warning, Wrong Package Received in UpStream, That could not happened!\n")
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} .elsewhen( upRecvStateCurr === UpRecvStateOHead & upRecvSteteNext === UpRecvStateIdle ){
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isUpStreamError := true.B
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printf("Warning, Wrong Package Received in UpStream, That could not happened!\n")
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} .elsewhen( upRecvStateCurr === UpRecvStateFData & upRecvSteteNext === UpRecvStateIdle ){
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isUpStreamError := true.B
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printf("Warning, Wrong Package Received in UpStream, That could not happened!\n")
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} .elsewhen( upRecvStateCurr === UpRecvStateCRC & (upRecvCnt > 3.U | (upStreamCdrIn.io.axis.fire & upStreamCdrIn.io.axis.bits.tlast & upRecvCnt < 3.U)) ){
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isUpStreamError := true.B
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printf("Warning, Wrong Package Received in UpStream, That could not happened!\n")
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}
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// val selfDataByte = Mux1H(Seq(
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// (downOldHead.operator === 0.U) -> OpInitByte,
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// (downOldHead.operator === 1.U) -> OpBoardCastByte,
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// (downOldHead.operator === 2.U) -> OpUniCastByte,
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// ))
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// val isDownStreamError = RegInit( false.B )
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// val forwardDataByte = downNewHead.length
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// when( downRecvStateCurr =/= downRecvSteteNext ){
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// downRecvCnt := 0.U
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// } .elsewhen( downStreamCdrIn.io.axis.fire ){
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// downRecvCnt := downRecvCnt + 1.U
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// }
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// //---------------
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// when( downRecvStateCurr === DownRecvStateOHead & downStreamCdrIn.io.axis.fire ){
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// downOldHead := Cat( downOldHead.asUInt.tail(8), downStreamCdrIn.io.axis.tdata ).asTypeOf(Header_Info_Bundle)
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// }
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// //---------------
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// val isNewHeadCreated = downRecvStateCurr === DownRecvStateSData & downRecvSteteNext === DownRecvStateFData //新头是由老头产生，担忧会欠拍
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// when( isNewHeadCreated ){
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// downNewHead.length := Mux( downOldHead.length >= selfDataByte, downOldHead.length - selfDataByte, 0.U )
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// downNewHead.operator := downOldHead.operator
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// downNewHead.param := downOldHead.param
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// }
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// when( downRecvStateCurr === DownRecvStateSData & downStreamCdrIn.io.axis.fire ){
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// downRegTemp(downRecvCnt) := downStreamCdrIn.io.axis.tdata
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// }
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// //---------------
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// downStreamFifo.io.enq.valid :=
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// downRecvStateCurr === DownRecvStateFData & downStreamCdrIn.io.axis.valid
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// downStreamFifo.io.enq.bits.tdata := downStreamCdrIn.io.axis.bits.tdata
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// downStreamFifo.io.enq.bits.tuser := downStreamCdrIn.io.axis.bits.tuser
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// downStreamFifo.io.enq.bits.tlast := downRecvCnt === (forwardDataByte -1.U) | downStreamCdrIn.io.axis.bits.tlast
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// downStreamCdrIn.io.axis.ready :=
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// (downRecvStateCurr === DownRecvStateOHead) |
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// (downRecvStateCurr === DownRecvStateSData) |
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// (downRecvStateCurr === DownRecvStateFData) |
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// (downRecvStateCurr === DownRecvStateCRC )
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// when( downRecvStateCurr === DownRecvStateIdle & downRecvSteteNext === DownRecvStateOHead){
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// isDownStreamError := false.B
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// } .elsewhen( downStreamFifo.io.enq.fire & downStreamFifo.io.enq.bits.tuser ){
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// isDownStreamError := true.B
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// printf("Warning, Wrong Package Received, That could not happened!\n")
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// } .elsewhen( downRecvStateCurr === DownRecvStateOHead & downRecvSteteNext === DownRecvStateOHead ){
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// isDownStreamError := true.B
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// printf("Warning, Wrong Package Received, That could not happened!\n")
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// } .elsewhen( downRecvStateCurr === DownRecvStateSHead & downRecvSteteNext === DownRecvStateOHead ){
|
||||
// isDownStreamError := true.B
|
||||
// printf("Warning, Wrong Package Received, That could not happened!\n")
|
||||
// } .elsewhen( downRecvStateCurr === DownRecvStateFHead & downRecvSteteNext === DownRecvStateOHead ){
|
||||
// isDownStreamError := true.B
|
||||
// printf("Warning, Wrong Package Received, That could not happened!\n")
|
||||
// } .elsewhen( downRecvStateCurr === DownRecvStateCRC & (downRecvCnt > 3.U | (downStreamCdrIn.io.axis.fire & downStreamCdrIn.io.axis.bits.tlast & downRecvCnt < 3.U)) ){
|
||||
// isDownStreamError := true.B
|
||||
// printf("Warning, Wrong Package Received, That could not happened!\n")
|
||||
// }
|
||||
|
||||
|
||||
|
||||
// assert( ~(downRecvStateCurr === DownRecvStateFData & ~downStreamFifo.io.enq.ready), "Assert Failed, downStream Forward Fifo is OverFlow!" )
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
assert( ~(upRecvStateCurr === UpRecvStateFData & ~upStreamFifo.io.enq.ready), "Assert Failed, upStream Forward Fifo is OverFlow!" )
|
||||
|
||||
|
||||
}
|
||||
|
||||
// trait ShinSlvPhyCloseLoop{ this: ShinSlvPhyBase =>
|
||||
trait ShinSlvPhyUpStreamSend{ this: ShinSlvPhyDownStream =>
|
||||
|
||||
|
||||
val UpSendStateIdle = 0.U
|
||||
val UpSendStateNHead = 1.U
|
||||
val UpSendStateLData = 2.U
|
||||
val UpSendStateFData = 3.U
|
||||
|
||||
|
||||
|
||||
val upSendSteteNext = Wire( UInt(3.W) )
|
||||
val upSendStateCurr = RegNext( downSendSteteNext, 0.U )
|
||||
|
||||
upSendSteteNext := Mux1H(Seq(
|
||||
( upSendStateCurr === UpSendStateIdle ) -> Mux( isUpNewHeadCreated, UpSendStateNHead, UpSendStateIdle ),
|
||||
( upSendStateCurr === UpSendStateNHead ) -> Mux( upSendCnt === ((headByte)-1).U & upStreamCdrOut.io.axis.fire, UpSendStateLData, UpSendStateNHead),
|
||||
( upSendStateCurr === UpSendStateLData ) -> Mux( upSendCnt === (upLocalDataByte - 1.U) & upStreamCdrOut.io.axis.fire, Mux( isLastDevice, UpSendStateIdle, UpSendStateFData), UpSendStateLData),
|
||||
( upSendStateCurr === UpSendStateFData ) -> Mux( upSendCnt === (upForwardDataByte - 1.U) & upStreamCdrOut.io.axis.fire, UpSendStateIdle, UpSendStateFData),
|
||||
))
|
||||
|
||||
when( upSendStateCurr =/= upSendSteteNext ){
|
||||
upSendCnt := 0.U
|
||||
} .elsewhen( upStreamCdrOut.io.axis.fire ){
|
||||
upSendCnt := upSendCnt + 1.U
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
upStreamCdrOut.io.axis.valid :=
|
||||
upSendStateCurr === UpSendStateNHead | upSendStateCurr === UpSendStateLData | upSendStateCurr === UpSendStateFData
|
||||
|
||||
upStreamCdrOut.io.axis.bits.tdata := Mux1H(Seq(
|
||||
( upSendStateCurr === UpSendStateNHead ) -> (upewHead.asUInt << (upSendCnt << 3)).head(8),
|
||||
( upSendStateCurr === UpSendStateLData ) -> upReg(upSendCnt),
|
||||
( upSendStateCurr === UpSendStateFData ) -> upStreamFifo.io.deq.bits.tdata,
|
||||
))
|
||||
|
||||
upStreamCdrOut.io.axis.bits.tlast := ( upSendStateCurr === UpSendStateFData ) & upStreamFifo.io.deq.bits.tlast
|
||||
|
||||
downStreamCdrOut.io.axis.bits.tuser :=
|
||||
(( upSendStateCurr === UpSendStateFData ) & upStreamFifo.io.deq.bits.tuser ) |
|
||||
isUpStreamError
|
||||
|
||||
upStreamFifo.io.deq.ready :=
|
||||
upSendStateCurr === UpSendStateFData & upStreamCdrOut.io.axis.ready
|
||||
|
||||
assert( ~(upStreamCdrIn.io.axis.valid & ~upStreamCdrIn.io.axis.ready) )
|
||||
|
||||
val isUpStreamEnd = (upSendStateCurr =/= UpSendStateIdle) & (upSendStateNext === UpSendStateIdle)
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
// trait ShinSlvPhyCloseLoop{ this: ShinSlvPhyDownStream =>
|
||||
// val isLastDevice: Bool
|
||||
|
||||
|
||||
// }
|
||||
|
||||
|
||||
abstract class ShinSlvLinkBase extends ShinSlvPhyBase
|
||||
abstract class ShinSlvLinkBase extends ShinSlvPhyDownStream
|
||||
with ShinSlvPhyDownStream
|
||||
with ShinSlvPhyUpStream
|
||||
// with ShinSlvPhyCloseLoop
|
||||
@@ -331,12 +411,89 @@ with ShinSlvPhyUpStream
|
||||
}
|
||||
|
||||
trait ShinSlvLinkInit{ this: ShinSlvLinkBase =>
|
||||
//定义初始化任务
|
||||
//下行定长包，各从机计算所在位置，更新ip地址寄存器，最后一个暂时通过IO实现闭环
|
||||
//以下行包头解析时间，从机位置号，标定数据计算更新RTC时间寄存器
|
||||
//上行根据包长，从站确定尾部伙伴数量（备用），
|
||||
//以上行包头解析时间放置本地时间
|
||||
//更新末尾寄存器
|
||||
|
||||
//热拔出 可以通过 io自动闭环，通过返回包缩短识别
|
||||
//热插入 必须带回寄存器信息，重新初始化，多发尾数据将被抛弃
|
||||
|
||||
//初始化应该下发 64*8 byte数据 对应 length = 512为slv0 504为slv1 ...
|
||||
|
||||
|
||||
val isInit = RegInit(false.B)
|
||||
val isLastInit = Reg(Bool())
|
||||
val slvID = Reg(UInt(7.W))
|
||||
val slvNum = Reg(UInt(7.W))
|
||||
val slvRTC = Reg(UInt(64.W))
|
||||
|
||||
val isLastDevice = isLastInit | io.isLast
|
||||
|
||||
val isLegalInitDownHead =
|
||||
downOldHead.operator === 0.U &
|
||||
downOldHead.length(2,0) === "b000".U
|
||||
|
||||
val isDownUpdate = RegInit(false.B)
|
||||
val isUpUpdate = RegInit(false.B)
|
||||
|
||||
when( (isDownNewHeadCreated | isLastDownStreamEnd) & isLegalInitDownHead ){
|
||||
slvID := 64.U - (downOldHead.length >> 3)
|
||||
isDownUpdate := true.B
|
||||
} .elsewhen( isUpStreamEnd ){
|
||||
isDownUpdate := false.B
|
||||
}
|
||||
|
||||
when( (isDownNewHeadCreated | isLastDownStreamEnd) & isLegalInitDownHead ){
|
||||
slvRTC := (64.U - (downOldHead.length >> 3)) << 5 // * 32
|
||||
} .otherwise{
|
||||
slvRTC := slvRTC + 1.U
|
||||
}
|
||||
|
||||
when( isLastDownStreamEnd & isLegalInitDownHead ){
|
||||
isLastInit := true.B
|
||||
} .elsewhen( isDownNewHeadCreated & isLegalInitDownHead ){
|
||||
isLastInit := false.B
|
||||
}
|
||||
|
||||
val isLegalInitUpHead =
|
||||
upOldHead.operator === 0.U &
|
||||
upOldHead.length(2,0) === "b000".U
|
||||
|
||||
when( isUpNewHeadCreated ){
|
||||
when( isLastDownStreamEnd ){
|
||||
slvNum := 65.U - (downOldHead.length >> 3)
|
||||
isUpUpdate := true.B
|
||||
} .elsewhen(isLegalInitUpHead){
|
||||
slvNum := (slvID + (upOldHead.length >> 3)) + 1.U
|
||||
isUpUpdate := true.B
|
||||
}
|
||||
} .elsewhen( isUpStreamEnd ){
|
||||
isUpUpdate := false.B
|
||||
}
|
||||
|
||||
when( isUpStreamEnd ){
|
||||
isInit := ~isDownStreamError & ~isUpStreamError & isDownUpdate & isUpUpdate
|
||||
}
|
||||
|
||||
val upRegMuxInit = isLegalInitUpHead
|
||||
when( upRegMuxInit ){
|
||||
upReg(0) := slvRTC(7,0)
|
||||
upReg(1) := slvRTC(15,8)
|
||||
upReg(2) := slvRTC(23,16)
|
||||
upReg(3) := slvRTC(31,24)
|
||||
upReg(4) := slvRTC(39,32)
|
||||
upReg(5) := slvRTC(47,40)
|
||||
upReg(6) := slvRTC(55,48)
|
||||
upReg(7) := slvRTC(63,56)
|
||||
}
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
trait ShinSlvLinkSync{ this: ShinSlvLinkBase =>
|
||||
|
||||
}
|
||||
|
||||
trait ShinSlvLinkBCast{ this: ShinSlvLinkBase =>
|
||||
|
||||
@@ -346,10 +503,11 @@ trait ShinSlvLinkUCast{ this: ShinSlvLinkBase =>
|
||||
|
||||
}
|
||||
|
||||
abstract class ShinSlvBase extends ShinSlvLinkBase
|
||||
class ShinSlvBase extends ShinSlvLinkBase
|
||||
with ShinSlvLinkInit
|
||||
with ShinSlvLinkSync
|
||||
with ShinSlvLinkBCast
|
||||
with ShinSlvLinkUCast
|
||||
with ShinSlvLinkUCast{
|
||||
assert( VecInit(upRegMuxInit).contains((x:Bool) = > (x === true.B)) <= 1.U, "Assert Failed, upReg Collision Used!\n" )
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -38,14 +38,24 @@ object testModule extends App {
|
||||
))
|
||||
|
||||
|
||||
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
|
||||
ChiselGeneratorAnnotation(() => { new CDROut })
|
||||
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
|
||||
// ChiselGeneratorAnnotation(() => { new CDROut })
|
||||
// ))
|
||||
|
||||
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
|
||||
// ChiselGeneratorAnnotation(() => { new CDRIn })
|
||||
// ))
|
||||
|
||||
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-E", "verilog" ) ++ args, Seq(
|
||||
ChiselGeneratorAnnotation(() => { new ShinMst })
|
||||
))
|
||||
|
||||
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
|
||||
ChiselGeneratorAnnotation(() => { new CDRIn })
|
||||
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-E", "verilog" ) ++ args, Seq(
|
||||
ChiselGeneratorAnnotation(() => { new ShinSlvBase })
|
||||
))
|
||||
|
||||
|
||||
|
||||
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
|
||||
// ChiselGeneratorAnnotation(() => { new BackPlaneChainTest })
|
||||
// ))
|
||||
|
||||
Reference in New Issue
Block a user