diff --git a/src/main/scala/backBoard/shin/ShinSlv.scala b/src/main/scala/backBoard/shin/ShinSlv.scala index 431f606..9bbf416 100644 --- a/src/main/scala/backBoard/shin/ShinSlv.scala +++ b/src/main/scala/backBoard/shin/ShinSlv.scala @@ -3,6 +3,27 @@ package BACK import chisel3._ import chisel3.util._ +class ShinSlvIO_Bundle extends Bundle{ + + val isOnline = Output(Bool()) + val isLast = Input(Bool()) + val DCIn = Input(Bool()) + + val downSer = new Bundle{ + val out = Output(Bool()) + val in = Input(Bool()) + } + val upSer = new Bundle{ + val out = Output(Bool()) + val in = Input(Bool()) + } + + + + + val overCLK = Input(Bool()) + +} abstract class ShinSlvPhyBase extends Module{ val downStreamCdrOut = Module(new CDROut) @@ -11,6 +32,17 @@ abstract class ShinSlvPhyBase extends Module{ val upStreamCdrOut = Module(new CDROut) val upStreamCdrIn = Module(new CDRIn ) + io.downSer.out := downStreamCdrOut.io.serDat + downStreamCdrIn.io.serDat := io.downSer.in + downStreamCdrIn.io.overCLK := io.overCLK + + io.upSer.out := upStreamCdrOut.io.serDat + upStreamCdrIn.io.serDat := io.upSer.in + upStreamCdrIn.io.overCLK := io.overCLK + + io.isOnline := true.B + + val downRegTemp = Reg(Vec( 32, UInt(8.W) )) val upReg = WireDefault(VecInit((0 until 32).map{i => 0.U(8.W)})) @@ -24,9 +56,11 @@ abstract class ShinSlvPhyBase extends Module{ val maxLocalByte = OpInitByte max OpBoardCastByte max OpUniCastByte + val isLastDevice: Bool + } -trait ShinSlvPhyDownStream{ this: ShinSlvPhyBase => +trait ShinSlvPhyDownStreamRecv{ this: ShinSlvPhyBase => val DownRecvStateIdle = 0.U val DownRecvStateOHead = 1.U @@ -35,10 +69,6 @@ trait ShinSlvPhyDownStream{ this: ShinSlvPhyBase => val DownRecvStateCRC = 4.U - val DownSendStateIdle = 0.U - val DownSendStateNHead = 1.U - val DownSendStateFData = 2.U - val downOldHead = Reg( new Header_Info_Bundle ) val downNewHead = Reg( new Header_Info_Bundle ) @@ -48,9 +78,9 @@ trait ShinSlvPhyDownStream{ this: ShinSlvPhyBase => val downRecvStateCurr = RegNext( downRecvSteteNext, 0.U ) val downRecvCnt = Reg(UInt(10.W)) - val downSendCnt = Reg(UInt(10.W)) - val selfDataByte = Mux1H(Seq( + + val downLocalDataByte = Mux1H(Seq( (downOldHead.operator === 0.U) -> OpInitByte, (downOldHead.operator === 1.U) -> OpBoardCastByte, (downOldHead.operator === 2.U) -> OpUniCastByte, @@ -58,14 +88,14 @@ trait ShinSlvPhyDownStream{ this: ShinSlvPhyBase => val isDownStreamError = RegInit( false.B ) - val forwardDataByte = downNewHead.length + val downForwardDataByte = downNewHead.length downRecvSteteNext := Mux1H(Seq( (downRecvStateCurr === DownRecvStateIdle ) -> Mux( downStreamCdrIn.io.axis.valid, DownRecvStateOHead, DownRecvStateIdle ), (downRecvStateCurr === DownRecvStateOHead) -> Mux( downStreamCdrIn.io.axis.fire, Mux( ~downStreamCdrIn.io.axis.bits.tlast, Mux(downRecvCnt === ((headByte)-1).U, DownRecvStateSData, DownRecvStateOHead), DownRecvStateIdle ), DownRecvStateOHead), - (downRecvStateCurr === DownRecvStateSData) -> Mux( downStreamCdrIn.io.axis.fire, Mux( ~downStreamCdrIn.io.axis.bits.tlast, Mux(downRecvCnt === (selfDataByte -1.U), DownRecvStateFData, DownRecvStateSData), DownRecvStateIdle ), DownRecvStateSData), - (downRecvStateCurr === DownRecvStateFData) -> Mux( downStreamCdrIn.io.axis.fire, Mux( ~downStreamCdrIn.io.axis.bits.tlast, Mux(downRecvCnt === (forwardDataByte -1.U) , DownRecvStateCRC, DownRecvStateFData), DownRecvStateIdle ), DownRecvStateFData), + (downRecvStateCurr === DownRecvStateSData) -> Mux( downStreamCdrIn.io.axis.fire, Mux( ~downStreamCdrIn.io.axis.bits.tlast, Mux(downRecvCnt === (downLocalDataByte -1.U), Mux( downRecvCnt === (downOldHead.length - 1.U), DownRecvStateCRC, DownRecvStateFData ), DownRecvStateSData), DownRecvStateIdle ), DownRecvStateSData), + (downRecvStateCurr === DownRecvStateFData) -> Mux( downStreamCdrIn.io.axis.fire, Mux( ~downStreamCdrIn.io.axis.bits.tlast, Mux(downRecvCnt === (downForwardDataByte -1.U) , DownRecvStateCRC, DownRecvStateFData), DownRecvStateIdle ), DownRecvStateFData), (downRecvStateCurr === DownRecvStateCRC ) -> Mux( downStreamCdrIn.io.axis.fire & downStreamCdrIn.io.axis.bits.tlast, DownRecvStateIdle, DownRecvStateCRC ), )) @@ -83,9 +113,9 @@ trait ShinSlvPhyDownStream{ this: ShinSlvPhyBase => //--------------- - val isNewHeadCreated = downRecvStateCurr === DownRecvStateSData & downRecvSteteNext === DownRecvStateFData //新头是由老头产生，担忧会欠拍 - when( isNewHeadCreated ){ - downNewHead.length := Mux( downOldHead.length >= selfDataByte, downOldHead.length - selfDataByte, 0.U ) + val isDownNewHeadCreated = downRecvStateCurr === DownRecvStateSData & downRecvSteteNext === DownRecvStateFData //新头是由老头产生，担忧会欠拍 + when( isDownNewHeadCreated ){ + downNewHead.length := Mux( downOldHead.length >= downLocalDataByte, downOldHead.length - downLocalDataByte, 0.U ) downNewHead.operator := downOldHead.operator downNewHead.param := downOldHead.param } @@ -97,34 +127,39 @@ trait ShinSlvPhyDownStream{ this: ShinSlvPhyBase => //--------------- downStreamFifo.io.enq.valid := - downRecvStateCurr === DownRecvStateFData & downStreamCdrIn.io.axis.valid + downRecvStateCurr === DownRecvStateFData & downStreamCdrIn.io.axis.fire & ~isLastDevice downStreamFifo.io.enq.bits.tdata := downStreamCdrIn.io.axis.bits.tdata downStreamFifo.io.enq.bits.tuser := downStreamCdrIn.io.axis.bits.tuser - downStreamFifo.io.enq.bits.tlast := downRecvCnt === (forwardDataByte -1.U) | downStreamCdrIn.io.axis.bits.tlast + downStreamFifo.io.enq.bits.tlast := downRecvCnt === (downForwardDataByte -1.U) | downStreamCdrIn.io.axis.bits.tlast downStreamCdrIn.io.axis.ready := (downRecvStateCurr === DownRecvStateOHead) | (downRecvStateCurr === DownRecvStateSData) | - (downRecvStateCurr === DownRecvStateFData) | + ((downRecvStateCurr === DownRecvStateFData) & downStreamFifo.io.enq.ready) | (downRecvStateCurr === DownRecvStateCRC ) when( downRecvStateCurr === DownRecvStateIdle & downRecvSteteNext === DownRecvStateOHead){ isDownStreamError := false.B } .elsewhen( downStreamFifo.io.enq.fire & downStreamFifo.io.enq.bits.tuser ){ isDownStreamError := true.B - printf("Warning, Wrong Package Received, That could not happened!\n") - } .elsewhen( downRecvStateCurr === DownRecvStateOHead & downRecvSteteNext === DownRecvStateOHead ){ + printf("Warning, Wrong Package Received in DownStream, That could not happened!\n") + } .elsewhen( downRecvStateCurr === DownRecvStateOHead & downRecvSteteNext === DownRecvStateIdle ){ isDownStreamError := true.B - printf("Warning, Wrong Package Received, That could not happened!\n") - } .elsewhen( downRecvStateCurr === DownRecvStateSHead & downRecvSteteNext === DownRecvStateOHead ){ + printf("Warning, Wrong Package Received in DownStream, That could not happened!\n") + } .elsewhen( downRecvStateCurr === DownRecvStateSHead & downRecvSteteNext === DownRecvStateIdle ){ isDownStreamError := true.B - printf("Warning, Wrong Package Received, That could not happened!\n") - } .elsewhen( downRecvStateCurr === DownRecvStateFHead & downRecvSteteNext === DownRecvStateOHead ){ + printf("Warning, Wrong Package Received in DownStream, That could not happened!\n") + } .elsewhen( downRecvStateCurr === DownRecvStateFHead & downRecvSteteNext === DownRecvStateIdle ){ isDownStreamError := true.B - printf("Warning, Wrong Package Received, That could not happened!\n") + printf("Warning, Wrong Package Received in DownStream, That could not happened!\n") } .elsewhen( downRecvStateCurr === DownRecvStateCRC & (downRecvCnt > 3.U | (downStreamCdrIn.io.axis.fire & downStreamCdrIn.io.axis.bits.tlast & downRecvCnt < 3.U)) ){ isDownStreamError := true.B - printf("Warning, Wrong Package Received, That could not happened!\n") + printf("Warning, Wrong Package Received in DownStream, That could not happened!\n") + } .elsewhen( isDownNewHeadCreated & downOldHead.length < downLocalDataByte ){ //本包的负载不能满足本级数据需求，传输错误 + isDownStreamError := true.B + printf("Warning, Wrong Package Received in DownStream, That could not happened!\n") + } .elsewhen( isLastDevice & downOldHead.length =/= downLocalDataByte ){ + printf("Warning, Wrong Package Received in DownStream, SoftWare Check!\n") } @@ -134,14 +169,23 @@ trait ShinSlvPhyDownStream{ this: ShinSlvPhyBase => +} + +trait ShinSlvPhyDownStreamSend{ this: ShinSlvPhyBase => + val DownSendStateIdle = 0.U + val DownSendStateNHead = 1.U + val DownSendStateFData = 2.U + + val downSendCnt = Reg(UInt(10.W)) + val downSendSteteNext = Wire( UInt(3.W) ) val downSendStateCurr = RegNext( downSendSteteNext, 0.U ) downSendSteteNext := Mux1H(Seq( - ( downSendStateCurr === DownSendStateIdle ) -> Mux( isNewHeadCreated, DownSendStateNHead, DownSendStateIdle ), + ( downSendStateCurr === DownSendStateIdle ) -> Mux( isDownNewHeadCreated & ~isLastDevice, DownSendStateNHead, DownSendStateIdle ), ( downSendStateCurr === DownSendStateNHead ) -> Mux( downSendCnt === ((headByte)-1).U & downStreamCdrOut.io.axis.fire, DownSendStateFData, DownSendStateNHead ), - ( downSendStateCurr === DownSendStateFData ) -> Mux( downSendCnt === (forwardDataByte -1.U) & downStreamCdrOut.io.axis.fire, DownSendStateIdle, DownSendStateFData), + ( downSendStateCurr === DownSendStateFData ) -> Mux( downSendCnt === (downForwardDataByte -1.U) & downStreamCdrOut.io.axis.fire, DownSendStateIdle, DownSendStateFData), )) when( downSendStateCurr =/= downSendSteteNext ){ @@ -168,22 +212,22 @@ trait ShinSlvPhyDownStream{ this: ShinSlvPhyBase => downStreamFifo.io.deq.ready := downSendStateCurr === DownSendStateFData & downStreamCdrOut.io.axis.ready - assert( ~(downStreamCdrIn.io.axis.valid & ~downStreamCdrIn.io.axis.ready) ) - + assert( ~(downStreamCdrIn.io.axis.valid & ~downStreamCdrIn.io.axis.ready) ) } -trait ShinSlvPhyUpStream{ this: ShinSlvPhyBase => +abstract ShinSlvPhyDownStream extends ShinSlvPhyBase +with ShinSlvPhyDownStreamRecv +with ShinSlvPhyDownStreamSend{ + +} + +trait ShinSlvPhyUpStreamRecv{ this: ShinSlvPhyDownStream => val UpRecvStateIdle = 0.U val UpRecvStateOHead = 1.U val UpRecvStateFData = 2.U val UpRecvStateCRC = 3.U - val UpSendStateIdle = 0.U - val UpSendStateNHead = 1.U - val UpSendStateSHead = 2.U - val UpSendStateFData = 3.U - val upOldHead = Reg( new Header_Info_Bundle ) val upNewHead = Reg( new Header_Info_Bundle ) @@ -210,119 +254,155 @@ trait ShinSlvPhyUpStream{ this: ShinSlvPhyBase => + val isLastDownStreamEnd = ( isLastDevice & (downRecvStateCurr === DownRecvStateCRC & downRecvStateNext === DownRecvStateIdle)) + + + //--------------- + + when( (upRecvStateCurr === UpRecvStateOHead & upStreamCdrIn.io.axis.fire) ){ + upOldHead := Cat( upOldHead.asUInt.tail(8), upStreamCdrIn.io.axis.tdata ).asTypeOf(Header_Info_Bundle) + } .elsewhen( isLastDownStreamEnd ){ + upOldHead.operator := downOldHead.operator + upOldHead.length := 0.U + upOldHead.param := downOldHead.param + } + //--------------- + + + val upLocalDataByte = Mux1H(Seq( + (upOldHead.operator === 0.U) -> OpInitByte, + (upOldHead.operator === 1.U) -> OpBoardCastByte, + (upOldHead.operator === 2.U) -> OpUniCastByte, + )) + + + + val isUpNewHeadCreated = + RegNext(upRecvStateCurr === UpRecvStateOHead & upRecvSteteNext === UpRecvStateFData, false.B) | //补一拍 + isLastDownStreamEnd + + when( isUpNewHeadCreated ){ + upNewHead.length := upOldHead.length + upLocalDataByte + upNewHead.operator := upOldHead.operator + upNewHead.param := upOldHead.param + } + + val upForwardDataByte = upNewHead.length + + + + //--------------- + upStreamFifo.io.enq.valid := + upRecvStateCurr === UpRecvStateFData & upStreamCdrIn.io.axis.fire + upStreamFifo.io.enq.bits.tdata := upStreamCdrIn.io.axis.bits.tdata + upStreamFifo.io.enq.bits.tuser := upStreamCdrIn.io.axis.bits.tuser + upStreamFifo.io.enq.bits.tlast := upRecvCnt === (upForwardDataByte -1.U) | upStreamCdrIn.io.axis.bits.tlast + + + upStreamCdrIn.io.axis.ready := + (upRecvStateCurr === UpRecvStateOHead) | + ((upRecvStateCurr === UpRecvStateFData) & upStreamFifo.io.enq.ready) | + (upRecvStateCurr === UpRecvStateCRC ) + val isUpStreamError = RegInit( false.B ) + + + when( (upRecvStateCurr === UpRecvStateIdle & upRecvSteteNext === UpRecvStateOHead) | isLastDownStreamEnd ){ + isUpStreamError := false.B + } .elsewhen( upStreamFifo.io.enq.fire & upStreamFifo.io.enq.bits.tuser ){ + isUpStreamError := true.B + printf("Warning, Wrong Package Received in UpStream, That could not happened!\n") + } .elsewhen( upRecvStateCurr === UpRecvStateOHead & upRecvSteteNext === UpRecvStateIdle ){ + isUpStreamError := true.B + printf("Warning, Wrong Package Received in UpStream, That could not happened!\n") + } .elsewhen( upRecvStateCurr === UpRecvStateFData & upRecvSteteNext === UpRecvStateIdle ){ + isUpStreamError := true.B + printf("Warning, Wrong Package Received in UpStream, That could not happened!\n") + } .elsewhen( upRecvStateCurr === UpRecvStateCRC & (upRecvCnt > 3.U | (upStreamCdrIn.io.axis.fire & upStreamCdrIn.io.axis.bits.tlast & upRecvCnt < 3.U)) ){ + isUpStreamError := true.B + printf("Warning, Wrong Package Received in UpStream, That could not happened!\n") + } - - -// val selfDataByte = Mux1H(Seq( -// (downOldHead.operator === 0.U) -> OpInitByte, -// (downOldHead.operator === 1.U) -> OpBoardCastByte, -// (downOldHead.operator === 2.U) -> OpUniCastByte, -// )) - -// val isDownStreamError = RegInit( false.B ) - -// val forwardDataByte = downNewHead.length - - -// when( downRecvStateCurr =/= downRecvSteteNext ){ -// downRecvCnt := 0.U -// } .elsewhen( downStreamCdrIn.io.axis.fire ){ -// downRecvCnt := downRecvCnt + 1.U -// } - -// //--------------- - -// when( downRecvStateCurr === DownRecvStateOHead & downStreamCdrIn.io.axis.fire ){ -// downOldHead := Cat( downOldHead.asUInt.tail(8), downStreamCdrIn.io.axis.tdata ).asTypeOf(Header_Info_Bundle) -// } - - -// //--------------- -// val isNewHeadCreated = downRecvStateCurr === DownRecvStateSData & downRecvSteteNext === DownRecvStateFData //新头是由老头产生，担忧会欠拍 -// when( isNewHeadCreated ){ -// downNewHead.length := Mux( downOldHead.length >= selfDataByte, downOldHead.length - selfDataByte, 0.U ) -// downNewHead.operator := downOldHead.operator -// downNewHead.param := downOldHead.param -// } - - -// when( downRecvStateCurr === DownRecvStateSData & downStreamCdrIn.io.axis.fire ){ -// downRegTemp(downRecvCnt) := downStreamCdrIn.io.axis.tdata -// } - -// //--------------- -// downStreamFifo.io.enq.valid := -// downRecvStateCurr === DownRecvStateFData & downStreamCdrIn.io.axis.valid -// downStreamFifo.io.enq.bits.tdata := downStreamCdrIn.io.axis.bits.tdata -// downStreamFifo.io.enq.bits.tuser := downStreamCdrIn.io.axis.bits.tuser -// downStreamFifo.io.enq.bits.tlast := downRecvCnt === (forwardDataByte -1.U) | downStreamCdrIn.io.axis.bits.tlast - -// downStreamCdrIn.io.axis.ready := -// (downRecvStateCurr === DownRecvStateOHead) | -// (downRecvStateCurr === DownRecvStateSData) | -// (downRecvStateCurr === DownRecvStateFData) | -// (downRecvStateCurr === DownRecvStateCRC ) - -// when( downRecvStateCurr === DownRecvStateIdle & downRecvSteteNext === DownRecvStateOHead){ -// isDownStreamError := false.B -// } .elsewhen( downStreamFifo.io.enq.fire & downStreamFifo.io.enq.bits.tuser ){ -// isDownStreamError := true.B -// printf("Warning, Wrong Package Received, That could not happened!\n") -// } .elsewhen( downRecvStateCurr === DownRecvStateOHead & downRecvSteteNext === DownRecvStateOHead ){ -// isDownStreamError := true.B -// printf("Warning, Wrong Package Received, That could not happened!\n") -// } .elsewhen( downRecvStateCurr === DownRecvStateSHead & downRecvSteteNext === DownRecvStateOHead ){ -// isDownStreamError := true.B -// printf("Warning, Wrong Package Received, That could not happened!\n") -// } .elsewhen( downRecvStateCurr === DownRecvStateFHead & downRecvSteteNext === DownRecvStateOHead ){ -// isDownStreamError := true.B -// printf("Warning, Wrong Package Received, That could not happened!\n") -// } .elsewhen( downRecvStateCurr === DownRecvStateCRC & (downRecvCnt > 3.U | (downStreamCdrIn.io.axis.fire & downStreamCdrIn.io.axis.bits.tlast & downRecvCnt < 3.U)) ){ -// isDownStreamError := true.B -// printf("Warning, Wrong Package Received, That could not happened!\n") -// } - - - -// assert( ~(downRecvStateCurr === DownRecvStateFData & ~downStreamFifo.io.enq.ready), "Assert Failed, downStream Forward Fifo is OverFlow!" ) - - - - - - - - - - - - - - - + assert( ~(upRecvStateCurr === UpRecvStateFData & ~upStreamFifo.io.enq.ready), "Assert Failed, upStream Forward Fifo is OverFlow!" ) } -// trait ShinSlvPhyCloseLoop{ this: ShinSlvPhyBase => +trait ShinSlvPhyUpStreamSend{ this: ShinSlvPhyDownStream => + + + val UpSendStateIdle = 0.U + val UpSendStateNHead = 1.U + val UpSendStateLData = 2.U + val UpSendStateFData = 3.U + + + + val upSendSteteNext = Wire( UInt(3.W) ) + val upSendStateCurr = RegNext( downSendSteteNext, 0.U ) + + upSendSteteNext := Mux1H(Seq( + ( upSendStateCurr === UpSendStateIdle ) -> Mux( isUpNewHeadCreated, UpSendStateNHead, UpSendStateIdle ), + ( upSendStateCurr === UpSendStateNHead ) -> Mux( upSendCnt === ((headByte)-1).U & upStreamCdrOut.io.axis.fire, UpSendStateLData, UpSendStateNHead), + ( upSendStateCurr === UpSendStateLData ) -> Mux( upSendCnt === (upLocalDataByte - 1.U) & upStreamCdrOut.io.axis.fire, Mux( isLastDevice, UpSendStateIdle, UpSendStateFData), UpSendStateLData), + ( upSendStateCurr === UpSendStateFData ) -> Mux( upSendCnt === (upForwardDataByte - 1.U) & upStreamCdrOut.io.axis.fire, UpSendStateIdle, UpSendStateFData), + )) + + when( upSendStateCurr =/= upSendSteteNext ){ + upSendCnt := 0.U + } .elsewhen( upStreamCdrOut.io.axis.fire ){ + upSendCnt := upSendCnt + 1.U + } + + + + + upStreamCdrOut.io.axis.valid := + upSendStateCurr === UpSendStateNHead | upSendStateCurr === UpSendStateLData | upSendStateCurr === UpSendStateFData + + upStreamCdrOut.io.axis.bits.tdata := Mux1H(Seq( + ( upSendStateCurr === UpSendStateNHead ) -> (upewHead.asUInt << (upSendCnt << 3)).head(8), + ( upSendStateCurr === UpSendStateLData ) -> upReg(upSendCnt), + ( upSendStateCurr === UpSendStateFData ) -> upStreamFifo.io.deq.bits.tdata, + )) + + upStreamCdrOut.io.axis.bits.tlast := ( upSendStateCurr === UpSendStateFData ) & upStreamFifo.io.deq.bits.tlast + + downStreamCdrOut.io.axis.bits.tuser := + (( upSendStateCurr === UpSendStateFData ) & upStreamFifo.io.deq.bits.tuser ) | + isUpStreamError + + upStreamFifo.io.deq.ready := + upSendStateCurr === UpSendStateFData & upStreamCdrOut.io.axis.ready + + assert( ~(upStreamCdrIn.io.axis.valid & ~upStreamCdrIn.io.axis.ready) ) + + val isUpStreamEnd = (upSendStateCurr =/= UpSendStateIdle) & (upSendStateNext === UpSendStateIdle) + +} + + + +// trait ShinSlvPhyCloseLoop{ this: ShinSlvPhyDownStream => +// val isLastDevice: Bool + // } -abstract class ShinSlvLinkBase extends ShinSlvPhyBase +abstract class ShinSlvLinkBase extends ShinSlvPhyDownStream with ShinSlvPhyDownStream with ShinSlvPhyUpStream // with ShinSlvPhyCloseLoop @@ -331,12 +411,89 @@ with ShinSlvPhyUpStream } trait ShinSlvLinkInit{ this: ShinSlvLinkBase => + //定义初始化任务 + //下行定长包，各从机计算所在位置，更新ip地址寄存器，最后一个暂时通过IO实现闭环 + //以下行包头解析时间，从机位置号，标定数据计算更新RTC时间寄存器 + //上行根据包长，从站确定尾部伙伴数量（备用）， + //以上行包头解析时间放置本地时间 + //更新末尾寄存器 + + //热拔出 可以通过 io自动闭环，通过返回包缩短识别 + //热插入 必须带回寄存器信息，重新初始化，多发尾数据将被抛弃 + + //初始化应该下发 64*8 byte数据 对应 length = 512为slv0 504为slv1 ... + + + val isInit = RegInit(false.B) + val isLastInit = Reg(Bool()) + val slvID = Reg(UInt(7.W)) + val slvNum = Reg(UInt(7.W)) + val slvRTC = Reg(UInt(64.W)) + + val isLastDevice = isLastInit | io.isLast + + val isLegalInitDownHead = + downOldHead.operator === 0.U & + downOldHead.length(2,0) === "b000".U + + val isDownUpdate = RegInit(false.B) + val isUpUpdate = RegInit(false.B) + + when( (isDownNewHeadCreated | isLastDownStreamEnd) & isLegalInitDownHead ){ + slvID := 64.U - (downOldHead.length >> 3) + isDownUpdate := true.B + } .elsewhen( isUpStreamEnd ){ + isDownUpdate := false.B + } + + when( (isDownNewHeadCreated | isLastDownStreamEnd) & isLegalInitDownHead ){ + slvRTC := (64.U - (downOldHead.length >> 3)) << 5 // * 32 + } .otherwise{ + slvRTC := slvRTC + 1.U + } + + when( isLastDownStreamEnd & isLegalInitDownHead ){ + isLastInit := true.B + } .elsewhen( isDownNewHeadCreated & isLegalInitDownHead ){ + isLastInit := false.B + } + + val isLegalInitUpHead = + upOldHead.operator === 0.U & + upOldHead.length(2,0) === "b000".U + + when( isUpNewHeadCreated ){ + when( isLastDownStreamEnd ){ + slvNum := 65.U - (downOldHead.length >> 3) + isUpUpdate := true.B + } .elsewhen(isLegalInitUpHead){ + slvNum := (slvID + (upOldHead.length >> 3)) + 1.U + isUpUpdate := true.B + } + } .elsewhen( isUpStreamEnd ){ + isUpUpdate := false.B + } + + when( isUpStreamEnd ){ + isInit := ~isDownStreamError & ~isUpStreamError & isDownUpdate & isUpUpdate + } + + val upRegMuxInit = isLegalInitUpHead + when( upRegMuxInit ){ + upReg(0) := slvRTC(7,0) + upReg(1) := slvRTC(15,8) + upReg(2) := slvRTC(23,16) + upReg(3) := slvRTC(31,24) + upReg(4) := slvRTC(39,32) + upReg(5) := slvRTC(47,40) + upReg(6) := slvRTC(55,48) + upReg(7) := slvRTC(63,56) + } + + } -trait ShinSlvLinkSync{ this: ShinSlvLinkBase => - -} trait ShinSlvLinkBCast{ this: ShinSlvLinkBase => @@ -346,10 +503,11 @@ trait ShinSlvLinkUCast{ this: ShinSlvLinkBase => } -abstract class ShinSlvBase extends ShinSlvLinkBase +class ShinSlvBase extends ShinSlvLinkBase with ShinSlvLinkInit -with ShinSlvLinkSync with ShinSlvLinkBCast -with ShinSlvLinkUCast +with ShinSlvLinkUCast{ + assert( VecInit(upRegMuxInit).contains((x:Bool) = > (x === true.B)) <= 1.U, "Assert Failed, upReg Collision Used!\n" ) +} diff --git a/src/test/scala/gcd/test.scala b/src/test/scala/gcd/test.scala index 3f34733..26d9a55 100644 --- a/src/test/scala/gcd/test.scala +++ b/src/test/scala/gcd/test.scala @@ -38,14 +38,24 @@ object testModule extends App { )) - (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq( - ChiselGeneratorAnnotation(() => { new CDROut }) + // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq( + // ChiselGeneratorAnnotation(() => { new CDROut }) + // )) + + // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq( + // ChiselGeneratorAnnotation(() => { new CDRIn }) + // )) + + (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-E", "verilog" ) ++ args, Seq( + ChiselGeneratorAnnotation(() => { new ShinMst }) )) - (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq( - ChiselGeneratorAnnotation(() => { new CDRIn }) + (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-E", "verilog" ) ++ args, Seq( + ChiselGeneratorAnnotation(() => { new ShinSlvBase }) )) + + // (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq( // ChiselGeneratorAnnotation(() => { new BackPlaneChainTest }) // ))