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从站初始化逻辑写完，准备编译开始第一轮测试

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RuigeLee
2024-10-15 17:37:53 +08:00
parent 96234875b0
commit f74cc355d4
2 changed files with 303 additions and 135 deletions
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18
src/test/scala/gcd/test.scala
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@@ -38,14 +38,24 @@ object testModule extends App {
))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new CDROut })
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
// ChiselGeneratorAnnotation(() => { new CDROut })
// ))
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
// ChiselGeneratorAnnotation(() => { new CDRIn })
// ))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-E", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new ShinMst })
))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new CDRIn })
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-E", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new ShinSlvBase })
))
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
// ChiselGeneratorAnnotation(() => { new BackPlaneChainTest })
// ))