sync包的定点替换 0x25寄存器

src/main/scala/backBoard/shin/SlaveParser.scala

@@ -46,8 +46,10 @@ class SlaveParserIO extends Bundle{
 
   val trigAddr = Input( Vec(8, UInt(15.W)) )
 
-  val timeStamp = Input(UInt(64.W))
+  val mstDeltaTimeStamp = Output(UInt(32.W))
   val isLoop = Output(Bool())
+
+  val cReg = Input(new CommonRegisterBundle)
 }
 
 abstract class SlaveParserBase extends Module{
@@ -534,7 +536,7 @@ trait SlaveParserSync{ this: SlaveParserBase =>
   val downTimeStamp = Reg(UInt(64.W)) //下行本地时间戳寄存器 
   val upTimeStamp   = Reg(UInt(64.W)) //上行本地时间戳寄存器
   val mstTimeStamp  = Reg(UInt(64.W)) //主站时间戳
-  val mstDeltaTimeStamp = Reg(UInt(32.W)) //主站时间戳差值
+  val mstDeltaTimeStamp = Reg(UInt(32.W)); io.mstDeltaTimeStamp := mstDeltaTimeStamp //主站时间戳差值
   val slvDeltaTimeStamp = Reg(UInt(32.W)) //从站时间戳差值
 
   val mstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主发从接时间差(中间变量)
@@ -555,13 +557,13 @@ trait SlaveParserSync{ this: SlaveParserBase =>
 
   //更新下行本地时间戳寄存器
   when( downRecParser.io.frameReq.fire ){
-    downTimeStamp := io.timeStamp
+    downTimeStamp := io.cReg.timeStamp
   }
 
   //更新上行本地时间戳寄存器
   when( upRecParser.io.frameReq.fire ){
-    upTimeStamp := io.timeStamp
-    slvDeltaTimeStamp := io.timeStamp - downTimeStamp
+    upTimeStamp := io.cReg.timeStamp
+    slvDeltaTimeStamp := io.cReg.timeStamp - downTimeStamp
   }
 
   //下行接收