diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index 6b9e9c5..79b57a9 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -5,6 +5,8 @@ import chisel3.util._ class CommonRegisterBundle extends Bundle{ val mstOrSlv = UInt(2.W) + def modeSel:Bool = mstOrSlv === "h1".U + val hwVersion = UInt(8.W) val hwSerial = UInt(48.W) val busRate = UInt(16.W) @@ -30,7 +32,7 @@ class CommonRegisterBundle extends Bundle{ // val wdtOverflow = UInt(8.W) val timeStamp = UInt(64.W) - // val deltaTime = UInt(32.W) + val mstDeltaTime = UInt(32.W) // val linkStatus = UInt(8.W) @@ -50,6 +52,8 @@ class MasterRegisterBundle extends Bundle{ val txLength = UInt(12.W) // val txStatus = UInt(16.W) + val rplTimeStampTx = UInt(16.W) + // val intEnable = UInt(8.W) // val intMask = UInt(8.W) @@ -100,7 +104,7 @@ class InterfaceIO extends Bundle{ - val modeSel = Output(Bool()) + // val modeSel = Output(Bool()) val txReq = Valid(new Bundle{ val txSM = UInt(2.W) @@ -115,10 +119,14 @@ class InterfaceIO extends Bundle{ val sram_w = Flipped(Vec( 4, new SRAM2kWRIO)) //QSPI val sram_r = Flipped(Vec( 4, new SRAM2kRDIO)) //QSPI - val timeStamp = Output(UInt(64.W)) + val cReg = Output(new CommonRegisterBundle) + val mReg = Output(new MasterRegisterBundle) + // val sReg = Output(new SlaveRegisterBundle) - val smEnqAddr = Output(Vec(8, UInt(16.W))) //触发SM切换缓冲区的地址 （或读或写） - val smDeqAddr = Output(Vec(8, UInt(16.W))) //触发SM切换缓冲区的地址 （或读或写） + + // val smEnqAddr = Output(Vec(8, UInt(16.W))) //触发SM切换缓冲区的地址 （或读或写） + // val smDeqAddr = Output(Vec(8, UInt(16.W))) //触发SM切换缓冲区的地址 （或读或写） + val mstDeltaTimeStamp = Input(UInt(32.W)) } @@ -133,10 +141,12 @@ abstract class InterfaceBase extends Module{ io.oqspi <> oQSpi.qspi io.iqspi <> iQSpi.qspi - val cReg = Wire(new CommonRegisterBundle) - val mReg = Wire(new MasterRegisterBundle) + val cReg = Wire(new CommonRegisterBundle); io.cReg := cReg + val mReg = Wire(new MasterRegisterBundle); io.mReg := mReg // val sReg = Wire(new SlaveRegisterBundle) + + val isSysInit = cReg.mstOrSlv =/= 0.U val isMstMode = cReg.mstOrSlv === "h1".U val isSlvMode = cReg.mstOrSlv === "h2".U @@ -159,18 +169,34 @@ abstract class InterfaceBase extends Module{ (addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ), (addr === "h21".U & isMstMode) -> mReg.txLength, + (addr === "h25".U & isMstMode) -> mReg.rplTimeStampTx(7,0), + (addr === "h26".U & isMstMode) -> mReg.rplTimeStampTx(15,8), + (addr === "h27".U ) -> cReg.spiSel ) ++ - ((0 until 16).map{ i => (addr === ("h80".U + i.U) ) -> cReg.encryptKey( 8*i+7,8*i+0 ) }) ++ - Seq() + Seq( + (addr === "h1c0".U ) -> cReg.timeStamp(7,0), + (addr === "h1c1".U ) -> cReg.timeStamp(15,8), + (addr === "h1c2".U ) -> cReg.timeStamp(23,16), + (addr === "h1c3".U ) -> cReg.timeStamp(31,24), + (addr === "h1c4".U ) -> cReg.timeStamp(39,32), + (addr === "h1c5".U ) -> cReg.timeStamp(47,40), + (addr === "h1c6".U ) -> cReg.timeStamp(55,48), + (addr === "h1c7".U ) -> cReg.timeStamp(63,56), + + (addr === "h1D0".U ) -> io.mstDeltaTimeStamp(7,0), + (addr === "h1D1".U ) -> io.mstDeltaTimeStamp(15,8), + (addr === "h1D2".U ) -> io.mstDeltaTimeStamp(23,16), + (addr === "h1D3".U ) -> io.mstDeltaTimeStamp(31,24), + ) ) } @@ -270,8 +296,11 @@ trait InterfaceMCUop{ this: InterfaceBase => mReg.rxSM := RegEnable( dataw(4,3), 0.U, isEnW & addrSel === "h20".U ) mReg.txLength := Cat( RegEnable( dataw, 0.U, isEnW & addrSel === "h22".U ), RegEnable( dataw, 0.U, isEnW & addrSel === "h21".U ) ) - - + mReg.rplTimeStampTx := + Cat( + RegEnable( dataw, 0.U, isEnW & addrSel === "h26".U ), + RegEnable( dataw, 0.U, isEnW & addrSel === "h25".U ) + ) @@ -345,8 +374,14 @@ trait InterfaceLVDSop{ this: InterfaceBase => trait InterfaceSync{ this: InterfaceBase => cReg.timeStamp := RegNext( cReg.timeStamp + 1.U, 0.U ) - io.timeStamp := cReg.timeStamp + cReg.mstDeltaTime := io.mstDeltaTimeStamp + // Cat( + //RegEnable( dataw, 0.U, isEnW & addrSel === "h1d3".U ), + //RegEnable( dataw, 0.U, isEnW & addrSel === "h1d2".U ), + //RegEnable( dataw, 0.U, isEnW & addrSel === "h1d1".U ), + //RegEnable( dataw, 0.U, isEnW & addrSel === "h1d0".U ), + // ) } class Interface extends InterfaceBase @@ -356,15 +391,14 @@ with InterfaceLVDSop with InterfaceSync { - io.modeSel := cReg.mstOrSlv === "h1".U io.txReq.bits.txSM := mReg.txSM io.txReq.bits.rxSM := mReg.rxSM io.txReq.bits.txLength := mReg.txLength io.txReq.valid := isEnW & addrSel === "h20".U & dataw.extract(0) === "b1".U //& mReg.txLength =/= 0.U - io.smEnqAddr := cReg.smEnqAddr - io.smDeqAddr := cReg.smDeqAddr + // io.smEnqAddr := cReg.smEnqAddr + // io.smDeqAddr := cReg.smDeqAddr } \ No newline at end of file diff --git a/src/main/scala/backBoard/shin/MasterParser.scala b/src/main/scala/backBoard/shin/MasterParser.scala index daa7ef4..9c5fc0e 100644 --- a/src/main/scala/backBoard/shin/MasterParser.scala +++ b/src/main/scala/backBoard/shin/MasterParser.scala @@ -21,7 +21,10 @@ class MasterParserIO extends Bundle{ val rxEnq = Output( Bool()) val txDeq = Output( Bool()) - val timeStamp = Input(UInt(64.W)) + val cReg = Input(new CommonRegisterBundle) + val mReg = Input(new MasterRegisterBundle) + + val deltaTimeStamp = Output(UInt(32.W)) } @@ -81,8 +84,40 @@ abstract class MasterParserBase extends Module{ io.sram_r.addrr := Mux( io.req.fire, 0.U, txAddr + 1.U ) io.downOut.valid := ~reqReady + + + val isRplTimeStamp = io.mReg.rplTimeStampTx.extract(15) + val isRplDeltaStamp = io.mReg.rplTimeStampTx.extract(14) + val rplCnt0 = io.mReg.rplTimeStampTx(10,0) + 0.U + val rplCnt1 = io.mReg.rplTimeStampTx(10,0) + 1.U + val rplCnt2 = io.mReg.rplTimeStampTx(10,0) + 2.U + val rplCnt3 = io.mReg.rplTimeStampTx(10,0) + 3.U + val rplCnt4 = io.mReg.rplTimeStampTx(10,0) + 4.U + val rplCnt5 = io.mReg.rplTimeStampTx(10,0) + 5.U + val rplCnt6 = io.mReg.rplTimeStampTx(10,0) + 6.U + val rplCnt7 = io.mReg.rplTimeStampTx(10,0) + 7.U + val rplCnt8 = io.mReg.rplTimeStampTx(10,0) + 8.U + val rplCnt9 = io.mReg.rplTimeStampTx(10,0) + 9.U + val rplCnt10 = io.mReg.rplTimeStampTx(10,0) + 10.U + val rplCnt11 = io.mReg.rplTimeStampTx(10,0) + 11.U + + io.downOut.bits.tdata := Mux1H(Seq( - ( txCnt < txLen ) -> io.sram_r.datar, + ( txCnt < txLen ) -> + MuxCase( io.sram_r.datar, Array( + ( isRplTimeStamp & ( txCnt === rplCnt0 ) ) -> io.cReg.timeStamp(7,0), + ( isRplTimeStamp & ( txCnt === rplCnt1 ) ) -> RegEnable(io.cReg.timeStamp(15,8), io.downOut.fire & txCnt === rplCnt0 ), + ( isRplTimeStamp & ( txCnt === rplCnt2 ) ) -> RegEnable(io.cReg.timeStamp(23,16), io.downOut.fire & txCnt === rplCnt0 ), + ( isRplTimeStamp & ( txCnt === rplCnt3 ) ) -> RegEnable(io.cReg.timeStamp(31,24), io.downOut.fire & txCnt === rplCnt0 ), + ( isRplTimeStamp & ( txCnt === rplCnt4 ) ) -> RegEnable(io.cReg.timeStamp(39,32), io.downOut.fire & txCnt === rplCnt0 ), + ( isRplTimeStamp & ( txCnt === rplCnt5 ) ) -> RegEnable(io.cReg.timeStamp(47,40), io.downOut.fire & txCnt === rplCnt0 ), + ( isRplTimeStamp & ( txCnt === rplCnt6 ) ) -> RegEnable(io.cReg.timeStamp(55,48), io.downOut.fire & txCnt === rplCnt0 ), + ( isRplTimeStamp & ( txCnt === rplCnt7 ) ) -> RegEnable(io.cReg.timeStamp(63,56), io.downOut.fire & txCnt === rplCnt0 ), + ( isRplDeltaStamp & ( txCnt === rplCnt8 ) ) -> io.cReg.mstDeltaTime(7,0), + ( isRplDeltaStamp & ( txCnt === rplCnt9 ) ) -> io.cReg.mstDeltaTime(15,8), + ( isRplDeltaStamp & ( txCnt === rplCnt10 ) ) -> io.cReg.mstDeltaTime(23,16), + ( isRplDeltaStamp & ( txCnt === rplCnt11 ) ) -> io.cReg.mstDeltaTime(31,24), + )), ( txCnt === txLen + 0.U ) -> txcrc.io.crc(31,24), ( txCnt === txLen + 1.U ) -> txcrc.io.crc(23,16), ( txCnt === txLen + 2.U ) -> txcrc.io.crc(15, 8), @@ -149,13 +184,14 @@ abstract class MasterParserBase extends Module{ class MasterParser extends MasterParserBase{ val deltaTimeStamp = Reg(UInt(32.W)) - dontTouch(deltaTimeStamp) + // dontTouch(deltaTimeStamp) + io.deltaTimeStamp := deltaTimeStamp val txStamps = Reg(UInt(32.W)) when( io.downOut.fire & io.downOut.bits.tlast ){ - txStamps := io.timeStamp(31,0) + txStamps := io.cReg.timeStamp(31,0) } .elsewhen( io.upIn.fire & io.upIn.bits.tlast & ~io.upIn.bits.tuser ){ - deltaTimeStamp := io.timeStamp(31,0) - txStamps + deltaTimeStamp := io.cReg.timeStamp(31,0) - txStamps } } \ No newline at end of file diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala index c4adf37..711d53e 100644 --- a/src/main/scala/backBoard/shin/ShinTop.scala +++ b/src/main/scala/backBoard/shin/ShinTop.scala @@ -70,7 +70,7 @@ abstract class ShinTopBase extends Module{ io.uDatOut := upCDROut.io.serDat //override - when( slaveParser.io.isLoop & interface.io.modeSel === false.B){ + when( slaveParser.io.isLoop & interface.io.cReg.modeSel === false.B){ upCDRIn.io.serDat := downCDROut.io.serDat io.dDatOut := false.B } @@ -209,8 +209,10 @@ abstract class ShinTopBase extends Module{ slaveParser.io.upOut.ready := false.B upCDROut.io.axis.valid := false.B upCDROut.io.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8)) - } + interface.io.mstDeltaTimeStamp := 0.U + + } } @@ -218,12 +220,12 @@ abstract class ShinTopBase extends Module{ trait ShinTopMaster{ this: ShinTopBase => - when( interface.io.modeSel === true.B ){ + when( interface.io.cReg.modeSel === true.B ){ masterParser.io.downOut <> downCDROut.io.axis masterParser.io.upIn <> upCDRIn.io.axis } - when( interface.io.modeSel === true.B ){ + when( interface.io.cReg.modeSel === true.B ){ when( interface.io.txReq.bits.rxSM === 0.U ){ smUnit(0).io.sram_w := masterParser.io.sram_w @@ -263,7 +265,7 @@ trait ShinTopMaster{ this: ShinTopBase => // _ := interface.io.smDeqAddr(7) - + interface.io.mstDeltaTimeStamp := masterParser.io.deltaTimeStamp } masterParser.io.req.valid := interface.io.txReq.valid @@ -271,37 +273,40 @@ trait ShinTopMaster{ this: ShinTopBase => io.rsp := masterParser.io.rsp - masterParser.io.timeStamp := interface.io.timeStamp + masterParser.io.cReg := interface.io.cReg + masterParser.io.mReg := interface.io.mReg + + } trait ShinTopSlave{ this: ShinTopBase => - when( interface.io.modeSel === false.B ){ + when( interface.io.cReg.modeSel === false.B ){ slaveParser.io.downIn <> downCDRIn.io.axis downCDROut.io.axis <> slaveParser.io.downOut slaveParser.io.upIn <> upCDRIn.io.axis upCDROut.io.axis <> slaveParser.io.upOut } - slaveParser.io.timeStamp := interface.io.timeStamp + slaveParser.io.cReg := interface.io.cReg - slaveParser.io.trigAddr(0) := interface.io.smEnqAddr(0) - slaveParser.io.trigAddr(1) := interface.io.smDeqAddr(1) - slaveParser.io.trigAddr(2) := interface.io.smEnqAddr(2) - slaveParser.io.trigAddr(3) := interface.io.smDeqAddr(3) - slaveParser.io.trigAddr(4) := interface.io.smEnqAddr(4) - slaveParser.io.trigAddr(5) := interface.io.smDeqAddr(5) - slaveParser.io.trigAddr(6) := interface.io.smEnqAddr(6) - slaveParser.io.trigAddr(7) := interface.io.smDeqAddr(7) + slaveParser.io.trigAddr(0) := interface.io.cReg.smEnqAddr(0) + slaveParser.io.trigAddr(1) := interface.io.cReg.smDeqAddr(1) + slaveParser.io.trigAddr(2) := interface.io.cReg.smEnqAddr(2) + slaveParser.io.trigAddr(3) := interface.io.cReg.smDeqAddr(3) + slaveParser.io.trigAddr(4) := interface.io.cReg.smEnqAddr(4) + slaveParser.io.trigAddr(5) := interface.io.cReg.smDeqAddr(5) + slaveParser.io.trigAddr(6) := interface.io.cReg.smEnqAddr(6) + slaveParser.io.trigAddr(7) := interface.io.cReg.smDeqAddr(7) - when( interface.io.modeSel === false.B ){ + when( interface.io.cReg.modeSel === false.B ){ smUnit(0).io.sram_w := slaveParser.io.sram_w(0) smUnit(2).io.sram_w := slaveParser.io.sram_w(1) smUnit(4).io.sram_w := slaveParser.io.sram_w(2) @@ -320,9 +325,11 @@ trait ShinTopSlave{ this: ShinTopBase => smUnit(1).io.deq := slaveParser.io.uSMdeq(0) smUnit(3).io.deq := slaveParser.io.uSMdeq(1) smUnit(5).io.deq := slaveParser.io.uSMdeq(2) - smUnit(7).io.deq := slaveParser.io.uSMdeq(3) - } + smUnit(7).io.deq := slaveParser.io.uSMdeq(3) + interface.io.mstDeltaTimeStamp := slaveParser.io.mstDeltaTimeStamp + + } } diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index ae8f5de..de12f62 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -46,8 +46,10 @@ class SlaveParserIO extends Bundle{ val trigAddr = Input( Vec(8, UInt(15.W)) ) - val timeStamp = Input(UInt(64.W)) + val mstDeltaTimeStamp = Output(UInt(32.W)) val isLoop = Output(Bool()) + + val cReg = Input(new CommonRegisterBundle) } abstract class SlaveParserBase extends Module{ @@ -534,7 +536,7 @@ trait SlaveParserSync{ this: SlaveParserBase => val downTimeStamp = Reg(UInt(64.W)) //下行本地时间戳寄存器 val upTimeStamp = Reg(UInt(64.W)) //上行本地时间戳寄存器 val mstTimeStamp = Reg(UInt(64.W)) //主站时间戳 - val mstDeltaTimeStamp = Reg(UInt(32.W)) //主站时间戳差值 + val mstDeltaTimeStamp = Reg(UInt(32.W)); io.mstDeltaTimeStamp := mstDeltaTimeStamp //主站时间戳差值 val slvDeltaTimeStamp = Reg(UInt(32.W)) //从站时间戳差值 val mstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主发从接时间差(中间变量) @@ -555,13 +557,13 @@ trait SlaveParserSync{ this: SlaveParserBase => //更新下行本地时间戳寄存器 when( downRecParser.io.frameReq.fire ){ - downTimeStamp := io.timeStamp + downTimeStamp := io.cReg.timeStamp } //更新上行本地时间戳寄存器 when( upRecParser.io.frameReq.fire ){ - upTimeStamp := io.timeStamp - slvDeltaTimeStamp := io.timeStamp - downTimeStamp + upTimeStamp := io.cReg.timeStamp + slvDeltaTimeStamp := io.cReg.timeStamp - downTimeStamp } //下行接收 diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index 6316db8..d3d43a7 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -415,7 +415,7 @@ initial begin #50000 #50000 #50000 - $display("index @ %d", s_ShinTop_Mst.interface__io_timeStamp); + $display("index @ %d", s_ShinTop_Mst.interface__io_cReg_timeStamp); begin @@ -463,7 +463,7 @@ initial begin #50000 #50000 #50000 - $display("read&write @ %d", s_ShinTop_Mst.interface__io_timeStamp); + $display("read&write @ %d", s_ShinTop_Mst.interface__io_cReg_timeStamp); begin @@ -579,7 +579,7 @@ initial begin #90000 #90000 - $display("sync @ %d", s_ShinTop_Mst.interface__io_timeStamp); + $display("sync @ %d", s_ShinTop_Mst.interface__io_cReg_timeStamp); begin @@ -621,6 +621,10 @@ initial begin spi_trans( (16'h1000), (`SPI_WRITE), (24), (0) ); //写入SM1 + //写入替换时间戳替换地址 + txBuf[0+3] = 8'h0c; + txBuf[1+3] = 8'hc0; + spi_trans( (16'h25), (`SPI_WRITE), (2), (0) ); //写入SM1 //发布请求 txBuf[0+3] = 8'h18;