ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

sync包的定点替换 0x25寄存器

Browse Source
This commit is contained in:
Ruige Lee
2025-05-15 14:57:58 +08:00
parent 30df59220f
commit f71b8553cb
5 changed files with 130 additions and 47 deletions
Download Patch File Download Diff File Expand all files Collapse all files

45
src/main/scala/backBoard/shin/ShinTop.scala
View File

@@ -70,7 +70,7 @@ abstract class ShinTopBase extends Module{
io.uDatOut := upCDROut.io.serDat
//override
when( slaveParser.io.isLoop & interface.io.modeSel === false.B){
when( slaveParser.io.isLoop & interface.io.cReg.modeSel === false.B){
upCDRIn.io.serDat := downCDROut.io.serDat
io.dDatOut := false.B
}
@@ -209,8 +209,10 @@ abstract class ShinTopBase extends Module{
slaveParser.io.upOut.ready := false.B
upCDROut.io.axis.valid := false.B
upCDROut.io.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
}
interface.io.mstDeltaTimeStamp := 0.U
}
}
@@ -218,12 +220,12 @@ abstract class ShinTopBase extends Module{
trait ShinTopMaster{ this: ShinTopBase =>
when( interface.io.modeSel === true.B ){
when( interface.io.cReg.modeSel === true.B ){
masterParser.io.downOut <> downCDROut.io.axis
masterParser.io.upIn <> upCDRIn.io.axis
}
when( interface.io.modeSel === true.B ){
when( interface.io.cReg.modeSel === true.B ){
when( interface.io.txReq.bits.rxSM === 0.U ){
smUnit(0).io.sram_w := masterParser.io.sram_w
@@ -263,7 +265,7 @@ trait ShinTopMaster{ this: ShinTopBase =>
// _ := interface.io.smDeqAddr(7)
interface.io.mstDeltaTimeStamp := masterParser.io.deltaTimeStamp
}
masterParser.io.req.valid := interface.io.txReq.valid
@@ -271,37 +273,40 @@ trait ShinTopMaster{ this: ShinTopBase =>
io.rsp := masterParser.io.rsp
masterParser.io.timeStamp := interface.io.timeStamp
masterParser.io.cReg := interface.io.cReg
masterParser.io.mReg := interface.io.mReg
}
trait ShinTopSlave{ this: ShinTopBase =>
when( interface.io.modeSel === false.B ){
when( interface.io.cReg.modeSel === false.B ){
slaveParser.io.downIn <> downCDRIn.io.axis
downCDROut.io.axis <> slaveParser.io.downOut
slaveParser.io.upIn <> upCDRIn.io.axis
upCDROut.io.axis <> slaveParser.io.upOut
}
slaveParser.io.timeStamp := interface.io.timeStamp
slaveParser.io.cReg := interface.io.cReg
slaveParser.io.trigAddr(0) := interface.io.smEnqAddr(0)
slaveParser.io.trigAddr(1) := interface.io.smDeqAddr(1)
slaveParser.io.trigAddr(2) := interface.io.smEnqAddr(2)
slaveParser.io.trigAddr(3) := interface.io.smDeqAddr(3)
slaveParser.io.trigAddr(4) := interface.io.smEnqAddr(4)
slaveParser.io.trigAddr(5) := interface.io.smDeqAddr(5)
slaveParser.io.trigAddr(6) := interface.io.smEnqAddr(6)
slaveParser.io.trigAddr(7) := interface.io.smDeqAddr(7)
slaveParser.io.trigAddr(0) := interface.io.cReg.smEnqAddr(0)
slaveParser.io.trigAddr(1) := interface.io.cReg.smDeqAddr(1)
slaveParser.io.trigAddr(2) := interface.io.cReg.smEnqAddr(2)
slaveParser.io.trigAddr(3) := interface.io.cReg.smDeqAddr(3)
slaveParser.io.trigAddr(4) := interface.io.cReg.smEnqAddr(4)
slaveParser.io.trigAddr(5) := interface.io.cReg.smDeqAddr(5)
slaveParser.io.trigAddr(6) := interface.io.cReg.smEnqAddr(6)
slaveParser.io.trigAddr(7) := interface.io.cReg.smDeqAddr(7)
when( interface.io.modeSel === false.B ){
when( interface.io.cReg.modeSel === false.B ){
smUnit(0).io.sram_w := slaveParser.io.sram_w(0)
smUnit(2).io.sram_w := slaveParser.io.sram_w(1)
smUnit(4).io.sram_w := slaveParser.io.sram_w(2)
@@ -320,9 +325,11 @@ trait ShinTopSlave{ this: ShinTopBase =>
smUnit(1).io.deq := slaveParser.io.uSMdeq(0)
smUnit(3).io.deq := slaveParser.io.uSMdeq(1)
smUnit(5).io.deq := slaveParser.io.uSMdeq(2)
smUnit(7).io.deq := slaveParser.io.uSMdeq(3)
}
smUnit(7).io.deq := slaveParser.io.uSMdeq(3)
interface.io.mstDeltaTimeStamp := slaveParser.io.mstDeltaTimeStamp
}
}