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sync包的定点替换 0x25寄存器

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This commit is contained in:
Ruige Lee
2025-05-15 14:57:58 +08:00
parent 30df59220f
commit f71b8553cb
5 changed files with 130 additions and 47 deletions
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46
src/main/scala/backBoard/shin/MasterParser.scala
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@@ -21,7 +21,10 @@ class MasterParserIO extends Bundle{
val rxEnq = Output( Bool())
val txDeq = Output( Bool())
val timeStamp = Input(UInt(64.W))
val cReg = Input(new CommonRegisterBundle)
val mReg = Input(new MasterRegisterBundle)
val deltaTimeStamp = Output(UInt(32.W))
}
@@ -81,8 +84,40 @@ abstract class MasterParserBase extends Module{
io.sram_r.addrr := Mux( io.req.fire, 0.U, txAddr + 1.U )
io.downOut.valid := ~reqReady
val isRplTimeStamp = io.mReg.rplTimeStampTx.extract(15)
val isRplDeltaStamp = io.mReg.rplTimeStampTx.extract(14)
val rplCnt0 = io.mReg.rplTimeStampTx(10,0) + 0.U
val rplCnt1 = io.mReg.rplTimeStampTx(10,0) + 1.U
val rplCnt2 = io.mReg.rplTimeStampTx(10,0) + 2.U
val rplCnt3 = io.mReg.rplTimeStampTx(10,0) + 3.U
val rplCnt4 = io.mReg.rplTimeStampTx(10,0) + 4.U
val rplCnt5 = io.mReg.rplTimeStampTx(10,0) + 5.U
val rplCnt6 = io.mReg.rplTimeStampTx(10,0) + 6.U
val rplCnt7 = io.mReg.rplTimeStampTx(10,0) + 7.U
val rplCnt8 = io.mReg.rplTimeStampTx(10,0) + 8.U
val rplCnt9 = io.mReg.rplTimeStampTx(10,0) + 9.U
val rplCnt10 = io.mReg.rplTimeStampTx(10,0) + 10.U
val rplCnt11 = io.mReg.rplTimeStampTx(10,0) + 11.U
io.downOut.bits.tdata := Mux1H(Seq(
( txCnt < txLen ) -> io.sram_r.datar,
( txCnt < txLen ) ->
MuxCase( io.sram_r.datar, Array(
( isRplTimeStamp & ( txCnt === rplCnt0 ) ) -> io.cReg.timeStamp(7,0),
( isRplTimeStamp & ( txCnt === rplCnt1 ) ) -> RegEnable(io.cReg.timeStamp(15,8), io.downOut.fire & txCnt === rplCnt0 ),
( isRplTimeStamp & ( txCnt === rplCnt2 ) ) -> RegEnable(io.cReg.timeStamp(23,16), io.downOut.fire & txCnt === rplCnt0 ),
( isRplTimeStamp & ( txCnt === rplCnt3 ) ) -> RegEnable(io.cReg.timeStamp(31,24), io.downOut.fire & txCnt === rplCnt0 ),
( isRplTimeStamp & ( txCnt === rplCnt4 ) ) -> RegEnable(io.cReg.timeStamp(39,32), io.downOut.fire & txCnt === rplCnt0 ),
( isRplTimeStamp & ( txCnt === rplCnt5 ) ) -> RegEnable(io.cReg.timeStamp(47,40), io.downOut.fire & txCnt === rplCnt0 ),
( isRplTimeStamp & ( txCnt === rplCnt6 ) ) -> RegEnable(io.cReg.timeStamp(55,48), io.downOut.fire & txCnt === rplCnt0 ),
( isRplTimeStamp & ( txCnt === rplCnt7 ) ) -> RegEnable(io.cReg.timeStamp(63,56), io.downOut.fire & txCnt === rplCnt0 ),
( isRplDeltaStamp & ( txCnt === rplCnt8 ) ) -> io.cReg.mstDeltaTime(7,0),
( isRplDeltaStamp & ( txCnt === rplCnt9 ) ) -> io.cReg.mstDeltaTime(15,8),
( isRplDeltaStamp & ( txCnt === rplCnt10 ) ) -> io.cReg.mstDeltaTime(23,16),
( isRplDeltaStamp & ( txCnt === rplCnt11 ) ) -> io.cReg.mstDeltaTime(31,24),
)),
( txCnt === txLen + 0.U ) -> txcrc.io.crc(31,24),
( txCnt === txLen + 1.U ) -> txcrc.io.crc(23,16),
( txCnt === txLen + 2.U ) -> txcrc.io.crc(15, 8),
@@ -149,13 +184,14 @@ abstract class MasterParserBase extends Module{
class MasterParser extends MasterParserBase{
val deltaTimeStamp = Reg(UInt(32.W))
dontTouch(deltaTimeStamp)
// dontTouch(deltaTimeStamp)
io.deltaTimeStamp := deltaTimeStamp
val txStamps = Reg(UInt(32.W))
when( io.downOut.fire & io.downOut.bits.tlast ){
txStamps := io.timeStamp(31,0)
txStamps := io.cReg.timeStamp(31,0)
} .elsewhen( io.upIn.fire & io.upIn.bits.tlast & ~io.upIn.bits.tuser ){
deltaTimeStamp := io.timeStamp(31,0) - txStamps
deltaTimeStamp := io.cReg.timeStamp(31,0) - txStamps
}
}