sync包的定点替换 0x25寄存器

src/main/scala/backBoard/shin/Interface.scala

@@ -5,6 +5,8 @@ import chisel3.util._
 
 class CommonRegisterBundle extends Bundle{
   val mstOrSlv  = UInt(2.W)
+  def modeSel:Bool = mstOrSlv === "h1".U
+
   val hwVersion = UInt(8.W)
   val hwSerial  = UInt(48.W)
   val busRate   = UInt(16.W)
@@ -30,7 +32,7 @@ class CommonRegisterBundle extends Bundle{
   // val wdtOverflow = UInt(8.W)
 
   val timeStamp = UInt(64.W)
-  // val deltaTime = UInt(32.W)
+  val mstDeltaTime = UInt(32.W)
 
   // val linkStatus = UInt(8.W)
 
@@ -50,6 +52,8 @@ class MasterRegisterBundle extends Bundle{
   val txLength     = UInt(12.W)
   // val txStatus     = UInt(16.W)
 
+  val rplTimeStampTx = UInt(16.W)
+
 
   // val intEnable    = UInt(8.W)
   // val intMask      = UInt(8.W)
@@ -100,7 +104,7 @@ class InterfaceIO extends Bundle{
 
 
 
-  val modeSel = Output(Bool())
+  // val modeSel = Output(Bool())
 
   val txReq = Valid(new Bundle{
     val txSM = UInt(2.W)
@@ -115,10 +119,14 @@ class InterfaceIO extends Bundle{
   val sram_w = Flipped(Vec( 4, new SRAM2kWRIO)) //QSPI
   val sram_r = Flipped(Vec( 4, new SRAM2kRDIO)) //QSPI
 
-  val timeStamp = Output(UInt(64.W))
+  val cReg = Output(new CommonRegisterBundle)
+  val mReg = Output(new MasterRegisterBundle)
+  // val sReg = Output(new SlaveRegisterBundle)
 
-  val smEnqAddr = Output(Vec(8, UInt(16.W))) //触发SM切换缓冲区的地址 （或读或写）
-  val smDeqAddr = Output(Vec(8, UInt(16.W))) //触发SM切换缓冲区的地址 （或读或写）
+
+  // val smEnqAddr = Output(Vec(8, UInt(16.W))) //触发SM切换缓冲区的地址 （或读或写）
+  // val smDeqAddr = Output(Vec(8, UInt(16.W))) //触发SM切换缓冲区的地址 （或读或写）
+  val mstDeltaTimeStamp = Input(UInt(32.W))
 }
 
 
@@ -133,10 +141,12 @@ abstract class InterfaceBase extends Module{
   io.oqspi <> oQSpi.qspi
   io.iqspi <> iQSpi.qspi
 
-  val cReg = Wire(new CommonRegisterBundle)
-  val mReg = Wire(new MasterRegisterBundle)
+  val cReg = Wire(new CommonRegisterBundle); io.cReg := cReg
+  val mReg = Wire(new MasterRegisterBundle); io.mReg := mReg
   // val sReg = Wire(new SlaveRegisterBundle)
 
+
+
   val isSysInit = cReg.mstOrSlv =/= 0.U
   val isMstMode = cReg.mstOrSlv === "h1".U
   val isSlvMode = cReg.mstOrSlv === "h2".U
@@ -159,18 +169,34 @@ abstract class InterfaceBase extends Module{
         (addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ),
         (addr === "h21".U & isMstMode) -> mReg.txLength,
 
+        (addr === "h25".U & isMstMode) -> mReg.rplTimeStampTx(7,0),
+        (addr === "h26".U & isMstMode) -> mReg.rplTimeStampTx(15,8),
+
         (addr === "h27".U ) -> cReg.spiSel
 
       ) ++
 
 
 
-
       ((0 until 16).map{ i =>
         (addr === ("h80".U + i.U) ) -> cReg.encryptKey( 8*i+7,8*i+0 )
       }) ++
 
-      Seq()
+      Seq(
+        (addr === "h1c0".U )  -> cReg.timeStamp(7,0),
+        (addr === "h1c1".U )  -> cReg.timeStamp(15,8),
+        (addr === "h1c2".U )  -> cReg.timeStamp(23,16),
+        (addr === "h1c3".U )  -> cReg.timeStamp(31,24),
+        (addr === "h1c4".U )  -> cReg.timeStamp(39,32),
+        (addr === "h1c5".U )  -> cReg.timeStamp(47,40),
+        (addr === "h1c6".U )  -> cReg.timeStamp(55,48),
+        (addr === "h1c7".U )  -> cReg.timeStamp(63,56),
+
+        (addr === "h1D0".U )  -> io.mstDeltaTimeStamp(7,0),  
+        (addr === "h1D1".U )  -> io.mstDeltaTimeStamp(15,8), 
+        (addr === "h1D2".U )  -> io.mstDeltaTimeStamp(23,16),
+        (addr === "h1D3".U )  -> io.mstDeltaTimeStamp(31,24),
+      )
 
     )
   }
@@ -270,8 +296,11 @@ trait InterfaceMCUop{ this: InterfaceBase =>
   mReg.rxSM     := RegEnable( dataw(4,3), 0.U, isEnW & addrSel === "h20".U )
   mReg.txLength := Cat( RegEnable( dataw, 0.U, isEnW & addrSel === "h22".U ), RegEnable( dataw, 0.U, isEnW & addrSel === "h21".U ) )
 
-
-
+  mReg.rplTimeStampTx := 
+    Cat(
+      RegEnable( dataw, 0.U, isEnW & addrSel === "h26".U ),
+      RegEnable( dataw, 0.U, isEnW & addrSel === "h25".U )
+    )
 
 
 
@@ -345,8 +374,14 @@ trait InterfaceLVDSop{ this: InterfaceBase =>
 
 trait InterfaceSync{ this: InterfaceBase =>
   cReg.timeStamp := RegNext( cReg.timeStamp + 1.U, 0.U )
-  io.timeStamp := cReg.timeStamp
 
+  cReg.mstDeltaTime := io.mstDeltaTimeStamp
+    // Cat(
+      //RegEnable( dataw, 0.U, isEnW & addrSel === "h1d3".U ),
+      //RegEnable( dataw, 0.U, isEnW & addrSel === "h1d2".U ),
+      //RegEnable( dataw, 0.U, isEnW & addrSel === "h1d1".U ),
+      //RegEnable( dataw, 0.U, isEnW & addrSel === "h1d0".U ),
+    // )
 }
 
 class Interface extends InterfaceBase
@@ -356,15 +391,14 @@ with InterfaceLVDSop
 with InterfaceSync
 {
 
-  io.modeSel := cReg.mstOrSlv === "h1".U
 
   io.txReq.bits.txSM  := mReg.txSM
   io.txReq.bits.rxSM  := mReg.rxSM
   io.txReq.bits.txLength := mReg.txLength
   io.txReq.valid := isEnW & addrSel === "h20".U & dataw.extract(0) === "b1".U //& mReg.txLength =/= 0.U
 
-  io.smEnqAddr := cReg.smEnqAddr
-  io.smDeqAddr := cReg.smDeqAddr
+  // io.smEnqAddr := cReg.smEnqAddr
+  // io.smDeqAddr := cReg.smDeqAddr
 
 
 }