处理中断服务

Makefile

@@ -38,21 +38,19 @@ VSimTop:
 	-y ${PWD}/tb/verilator/ \
 	--top-module SimTop \
 	--trace-fst \
-	--no-timing \
 	--cc ./tb/verilator/SimTop.v  \
 	--cc ${PWD}/generated/Rtpp/behav_srams.v  \
 	--cc ${PWD}/generated/Rtpp/RtppConfig.v  \
 	+define+RANDOMIZE_GARBAGE_ASSIGN \
 	+define+RANDOMIZE_INVALID_ASSIGN \
 	+define+RANDOMIZE_REG_INIT \
-	+define+RANDOMIZE_MEM_INIT \
 	+define+RANDOMIZE_DELAY=0 \
 	--exe --build \
 	${PWD}/tb/verilator/sim_main.cpp \
 	-Mdir ./tb/build/ \
 	-j 30
 
-
+	# +define+RANDOMIZE_MEM_INIT
 
 test:
 	./tb/build/VSimTop -w -l -f ./tb/sw/build/mstTest

tb/sw/src/MstMain.c

@@ -5,27 +5,44 @@
 // #include "timer.h"
 #include "tl2cdr.h"
 
+volatile uint32_t *plic_priority_3   = (uint32_t*)( 0xc000000U + 0X000004 * 3);
+volatile uint32_t *plic_priority_4   = (uint32_t*)( 0xc000000U + 0X000004 * 4);
+volatile uint32_t *plic_priority_5   = (uint32_t*)( 0xc000000U + 0X000004 * 5);
+volatile uint32_t *plic_priority_6   = (uint32_t*)( 0xc000000U + 0X000004 * 6);
+
+
 volatile uint32_t *plic_pending_0_31 = (uint32_t*)( 0xc000000U + 0X001000 );
 volatile uint32_t *plic_enable_0_31  = (uint32_t*)( 0xc000000U + 0X002000 );
+
+volatile uint32_t *plic_threshold_0  = (uint32_t*)( 0xc000000U + 0X200000 );
 volatile uint32_t *plic_claim        = (uint32_t*)( 0xc000000U + 0X200004 );
 
 
-uint32_t flag_intTxEnd = 0;
+volatile uint32_t flag_intTxEnd = 0;
-uint32_t flag_intRxError = 0;
+volatile uint32_t flag_intRxError = 0;
-uint32_t flag_intRxStart = 0;
+volatile uint32_t flag_intRxStart = 0;
-uint32_t flag_intRxEnd = 0;
+volatile uint32_t flag_intRxEnd = 0;
 
 
-void trap_entry(){
+void plic_handle(){
-	if( *plic_claim == 3 ){
+
+	
+	// 从 PLIC 中获取中断源 ID
+    uint32_t claim = *plic_claim;
+
+
+	if( claim == 3 ){
 		flag_intTxEnd = 1;
-	} else if( *plic_claim == 4 ){
+	} else if( claim == 4 ){
 		flag_intRxError = 1;
-	} else if( *plic_claim == 5 ){
+	} else if( claim == 5 ){
 		flag_intRxStart = 1;
-	} else if( *plic_claim == 6 ){
+	} else if( claim == 6 ){
 		flag_intRxEnd = 1;
 	}
+
+    // 通知 PLIC 完成中断处理
+    *plic_claim = claim;
 	return;
 }
 
@@ -62,6 +79,11 @@ void main()
 	uint32_t led = 0;
 
 	*plic_enable_0_31 = 1 << 3 | 1 << 4 | 1 << 5 | 1 << 6;
+	*plic_priority_3 = 1;
+	*plic_priority_4 = 1;
+	*plic_priority_5 = 1;
+	*plic_priority_6 = 1;
+	*plic_threshold_0 = 0;
 
 
 		*cdr_softReset = 1; //复位脉冲
@@ -69,16 +91,16 @@ void main()
 
 		register uint32_t flag;
 
-		asm volatile ( //timer 2s
+									// asm volatile ( //timer 2s
-			"1:\n"
+									// 	"1:\n"
-			"rdcycle %0\n"
+									// 	"rdcycle %0\n"
-			// "srli %0, %0, 12\n"
+									// 	// "srli %0, %0, 12\n"
-			"srli %0, %0, 27\n"
+									// 	"srli %0, %0, 27\n"
-			// "srli %0, %0, 26\n"
+									// 	// "srli %0, %0, 26\n"
-			"andi %0, %0, 0x1\n"
+									// 	"andi %0, %0, 0x1\n"
-			"beqz %0, 1b\n"
+									// 	"beqz %0, 1b\n"
-			:"+r"(flag)
+									// 	:"+r"(flag)
-		);
+									// );
 
 		// if( led ){
 		// 	*WriteGpio = 0xFFFFFFFF;

tb/sw/src/mstStartup.S

@@ -2,8 +2,8 @@
 
 
 .extern main
-.extern trap_entry
+.extern plic_handle
-.globl _prog_start
+.globl prog_start
 .section .text.init
 
 
@@ -11,6 +11,12 @@ _prog_start:
 
 	la t0, trap_entry
 	csrw mtvec, t0
+	li t0, 1 << 11
+	csrw mie, t0
+
+	csrr t0, mstatus
+	ori t0, t0, 1<<3
+	csrw mstatus, t0
 
 	li x1,  0
 	li x2,  0
@@ -51,9 +57,98 @@ _prog_start:
 
 
 
-# .balign 32
+.balign 32
-# .section .trap_entry, "ax", %progbits
+.section .trap_entry, "ax", %progbits
-# trap_entry:
+trap_entry:
+
+	addi	sp,sp,-136
+	sw	ra,4(sp)
+	sw	sp,8(sp)
+	sw	gp,12(sp)
+	sw	tp,16(sp)
+	sw	t0,20(sp)
+	sw	t1,24(sp)
+	sw	t2,28(sp)
+	sw	s0,32(sp)
+	sw	s1,36(sp)
+	sw	a0,40(sp)
+	sw	a1,44(sp)
+	sw	a2,48(sp)
+	sw	a3,52(sp)
+	sw	a4,56(sp)
+	sw	a5,60(sp)
+	sw	a6,64(sp)
+	sw	a7,68(sp)
+	sw	s2,72(sp)
+	sw	s3,76(sp)
+	sw	s4,80(sp)
+	sw	s5,84(sp)
+	sw	s6,88(sp)
+	sw	s7,92(sp)
+	sw	s8,96(sp)
+	sw	s9,100(sp)
+	sw	s10,104(sp)
+	sw	s11,108(sp)
+	sw	t3,112(sp)
+	sw	t4,116(sp)
+	sw	t5,120(sp)
+	sw	t6,124(sp)
+
+
+
+
+    csrr t0, mstatus            # 读取 mstatus 寄存器
+    andi t0, t0, ~(1 << 3)      # 清除 MIE 位 (全局中断禁用)
+    csrw mstatus, t0            # 写回 mstatus 寄存器
+
+
+
+	call plic_handle
+
+	csrr t0, mstatus
+	ori t0, t0, 1<<3
+	csrw mstatus, t0
+
+
+
+
+
+	lw	ra,4(sp)
+	lw	sp,8(sp)
+	lw	gp,12(sp)
+	lw	tp,16(sp)
+	lw	t0,20(sp)
+	lw	t1,24(sp)
+	lw	t2,28(sp)
+	lw	s0,32(sp)
+	lw	s1,36(sp)
+	lw	a0,40(sp)
+	lw	a1,44(sp)
+	lw	a2,48(sp)
+	lw	a3,52(sp)
+	lw	a4,56(sp)
+	lw	a5,60(sp)
+	lw	a6,64(sp)
+	lw	a7,68(sp)
+	lw	s2,72(sp)
+	lw	s3,76(sp)
+	lw	s4,80(sp)
+	lw	s5,84(sp)
+	lw	s6,88(sp)
+	lw	s7,92(sp)
+	lw	s8,96(sp)
+	lw	s9,100(sp)
+	lw	s10,104(sp)
+	lw	s11,108(sp)
+	lw	t3,112(sp)
+	lw	t4,116(sp)
+	lw	t5,120(sp)
+	lw	t6,124(sp)
+	addi	sp,sp,136
+
+
+
+	mret
 
 
 

tb/verilator/SimTop.v

@@ -84,7 +84,7 @@ ExampleRocketSystem s_rocket_mst(
   .cdrio_dDatOut(dDatSer[0])
 );
 
-
+/*
 ExampleRocketSystem s_rocket_slv0(
   .clock(clock),
   .reset(reset),
@@ -254,7 +254,7 @@ ExampleRocketSystem s_rocket_slv2(
   .cdrio_dDatIn(dDatSer[2]),
   .cdrio_dDatOut()
 );
-
+*/
 
 
 
@@ -337,14 +337,6 @@ integer i;
 initial begin
 
 #20
-	// if ( $value$plusargs("%s",testName) ) begin
-	// 	$display("%s",testName);
-	//   $readmemh(testName, mem);		
-	// end
-	// else begin 
-  //   $display("%s",testName);
-	// 	$error("Failed to read Files!");
-	// end
 
   $readmemh("./tb/sw/build/mstTest.verilog", mem0);
 	for ( i = 0; i < DP; i = i + 1 ) begin
@@ -355,38 +347,38 @@ initial begin
       `MEM0[i] = 32'h0;
     end
 
-    $display("%x",`MEM0[i]);
+    // $display("MEM0[%d] = %h", i, `MEM0[i]);
 	end
 
-  $readmemh("./tb/sw/build/slvTest.verilog", mem1);
+  // $readmemh("./tb/sw/build/slvTest.verilog", mem1);
-	for ( i = 0; i < DP; i = i + 1 ) begin
+	// for ( i = 0; i < DP; i = i + 1 ) begin
-    if ( mem1[i*4+0] || mem1[i*4+1] || mem1[i*4+2] || mem1[i*4+3] ) begin
+  //   if ( mem1[i*4+0] || mem1[i*4+1] || mem1[i*4+2] || mem1[i*4+3] ) begin
-      `MEM1[i] = {mem1[i*4+3], mem1[i*4+2], mem1[i*4+1], mem1[i*4+0]};
+  //     `MEM1[i] = {mem1[i*4+3], mem1[i*4+2], mem1[i*4+1], mem1[i*4+0]};
-    end
+  //   end
-    else begin
+  //   else begin
-      `MEM1[i] = 32'h0;
+  //     `MEM1[i] = 32'h0;
-    end
+  //   end
-	end
+	// end
 
-  $readmemh("./tb/sw/build/slvTest.verilog", mem2);
+  // $readmemh("./tb/sw/build/slvTest.verilog", mem2);
-	for ( i = 0; i < DP; i = i + 1 ) begin
+	// for ( i = 0; i < DP; i = i + 1 ) begin
-    if ( mem2[i*4+0] || mem2[i*4+1] || mem2[i*4+2] || mem2[i*4+3] ) begin
+  //   if ( mem2[i*4+0] || mem2[i*4+1] || mem2[i*4+2] || mem2[i*4+3] ) begin
-      `MEM2[i] = {mem2[i*4+3], mem2[i*4+2], mem2[i*4+1], mem2[i*4+0]};
+  //     `MEM2[i] = {mem2[i*4+3], mem2[i*4+2], mem2[i*4+1], mem2[i*4+0]};
-    end
+  //   end
-    else begin
+  //   else begin
-      `MEM2[i] = 32'h0;
+  //     `MEM2[i] = 32'h0;
-    end
+  //   end
-	end
+	// end
 
-    $readmemh("./tb/sw/build/slvTest.verilog", mem3);
+  //   $readmemh("./tb/sw/build/slvTest.verilog", mem3);
-	for ( i = 0; i < DP; i = i + 1 ) begin
+	// for ( i = 0; i < DP; i = i + 1 ) begin
-    if ( mem3[i*4+0] || mem3[i*4+1] || mem3[i*4+2] || mem3[i*4+3] ) begin
+  //   if ( mem3[i*4+0] || mem3[i*4+1] || mem3[i*4+2] || mem3[i*4+3] ) begin
-      `MEM3[i] = {mem3[i*4+3], mem3[i*4+2], mem3[i*4+1], mem3[i*4+0]};
+  //     `MEM3[i] = {mem3[i*4+3], mem3[i*4+2], mem3[i*4+1], mem3[i*4+0]};
-    end
+  //   end
-    else begin
+  //   else begin
-      `MEM3[i] = 32'h0;
+  //     `MEM3[i] = 32'h0;
-    end
+  //   end
-	end
+	// end
 
 end
 

tb/verilator/sim_main.cpp

@@ -140,7 +140,7 @@ int main(int argc, char **argv, char **env) {
 #endif
 
 		if ( flag_limitEnable ) {
-			if ( main_cycle > 3000 ){
+			if ( main_cycle > 30000 ){
 				std::cout << "Timeout!!!!!" << std::endl;	
 				sim_exit();
 				return -1;