394 lines
8.5 KiB
Verilog
394 lines
8.5 KiB
Verilog
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module SimTop (
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// output success,
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// output fail,
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input clock, //100MHz
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input reset,
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input clk400
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);
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wire [3:0] uDatSer;
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wire [3:0] dDatSer;
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wire [3:0] dmactive;
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ExampleRocketSystem s_rocket_mst(
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.clock(clock),
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.reset(reset),
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.resetctrl_hartIsInReset_0(reset),
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.debug_clock(clock),
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.debug_reset(reset),
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.debug_systemjtag_jtag_TCK(1'b0),
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.debug_systemjtag_jtag_TMS(1'b0),
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.debug_systemjtag_jtag_TDI(1'b0),
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.debug_systemjtag_jtag_TDO_data(),
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.debug_systemjtag_jtag_TDO_driven(),
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.debug_systemjtag_reset(reset),
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.debug_systemjtag_mfr_id(11'b0),
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.debug_systemjtag_part_number(16'b0),
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.debug_systemjtag_version(4'b0),
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.debug_ndreset(),
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.debug_dmactive(dmactive[0]),
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.debug_dmactiveAck(dmactive[0]),
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.mmio_apb_0_psel(),
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.mmio_apb_0_penable(),
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.mmio_apb_0_pwrite(),
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.mmio_apb_0_paddr(),
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.mmio_apb_0_pprot(),
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.mmio_apb_0_pwdata(),
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.mmio_apb_0_pstrb(),
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.mmio_apb_0_pready(1'b1),
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.mmio_apb_0_pslverr(1'b0),
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.mmio_apb_0_prdata(32'b0),
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.mmio_ahb_0_hmastlock(),
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.mmio_ahb_0_hsel(),
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.mmio_ahb_0_hready(),
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.mmio_ahb_0_hreadyout(1'b1),
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.mmio_ahb_0_htrans(),
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.mmio_ahb_0_hsize(),
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.mmio_ahb_0_hburst(),
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.mmio_ahb_0_hwrite(),
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.mmio_ahb_0_hprot(),
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.mmio_ahb_0_haddr(),
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.mmio_ahb_0_hwdata(),
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.mmio_ahb_0_hresp(2'b0),
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.mmio_ahb_0_hrdata(32'b0),
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.mmio_ahb_0_hmaster(),
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.mmio_ahb_0_hsplit(16'b0),
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.interrupts(2'b0),
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.cdrio_overCLK(clk400),
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.cdrio_uDatIn(uDatSer[0]),
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.cdrio_uDatOut(),
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.cdrio_dDatIn(1'b0),
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.cdrio_dDatOut(dDatSer[0])
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);
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/*
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ExampleRocketSystem s_rocket_slv0(
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.clock(clock),
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.reset(reset),
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.resetctrl_hartIsInReset_0(reset),
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.debug_clock(clock),
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.debug_reset(reset),
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.debug_systemjtag_jtag_TCK(1'b0),
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.debug_systemjtag_jtag_TMS(1'b0),
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.debug_systemjtag_jtag_TDI(1'b0),
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.debug_systemjtag_jtag_TDO_data(),
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.debug_systemjtag_jtag_TDO_driven(),
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.debug_systemjtag_reset(reset),
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.debug_systemjtag_mfr_id(11'b0),
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.debug_systemjtag_part_number(16'b0),
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.debug_systemjtag_version(4'b0),
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.debug_ndreset(),
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.debug_dmactive(dmactive[1]),
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.debug_dmactiveAck(dmactive[1]),
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.mmio_apb_0_psel(),
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.mmio_apb_0_penable(),
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.mmio_apb_0_pwrite(),
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.mmio_apb_0_paddr(),
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.mmio_apb_0_pprot(),
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.mmio_apb_0_pwdata(),
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.mmio_apb_0_pstrb(),
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.mmio_apb_0_pready(1'b1),
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.mmio_apb_0_pslverr(1'b0),
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.mmio_apb_0_prdata(32'b0),
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.mmio_ahb_0_hmastlock(),
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.mmio_ahb_0_hsel(),
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.mmio_ahb_0_hready(),
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.mmio_ahb_0_hreadyout(1'b1),
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.mmio_ahb_0_htrans(),
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.mmio_ahb_0_hsize(),
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.mmio_ahb_0_hburst(),
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.mmio_ahb_0_hwrite(),
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.mmio_ahb_0_hprot(),
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.mmio_ahb_0_haddr(),
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.mmio_ahb_0_hwdata(),
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.mmio_ahb_0_hresp(2'b0),
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.mmio_ahb_0_hrdata(32'b0),
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.mmio_ahb_0_hmaster(),
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.mmio_ahb_0_hsplit(16'b0),
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.interrupts(2'b0),
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.cdrio_overCLK(clk400),
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.cdrio_uDatIn(uDatSer[1]),
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.cdrio_uDatOut(uDatSer[0]),
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.cdrio_dDatIn(dDatSer[0]),
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.cdrio_dDatOut(dDatSer[1])
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);
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ExampleRocketSystem s_rocket_slv1(
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.clock(clock),
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.reset(reset),
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.resetctrl_hartIsInReset_0(reset),
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.debug_clock(clock),
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.debug_reset(reset),
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.debug_systemjtag_jtag_TCK(1'b0),
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.debug_systemjtag_jtag_TMS(1'b0),
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.debug_systemjtag_jtag_TDI(1'b0),
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.debug_systemjtag_jtag_TDO_data(),
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.debug_systemjtag_jtag_TDO_driven(),
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.debug_systemjtag_reset(reset),
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.debug_systemjtag_mfr_id(11'b0),
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.debug_systemjtag_part_number(16'b0),
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.debug_systemjtag_version(4'b0),
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.debug_ndreset(),
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.debug_dmactive(dmactive[2]),
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.debug_dmactiveAck(dmactive[2]),
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.mmio_apb_0_psel(),
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.mmio_apb_0_penable(),
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.mmio_apb_0_pwrite(),
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.mmio_apb_0_paddr(),
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.mmio_apb_0_pprot(),
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.mmio_apb_0_pwdata(),
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.mmio_apb_0_pstrb(),
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.mmio_apb_0_pready(1'b1),
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.mmio_apb_0_pslverr(1'b0),
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.mmio_apb_0_prdata(32'b0),
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.mmio_ahb_0_hmastlock(),
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.mmio_ahb_0_hsel(),
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.mmio_ahb_0_hready(),
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.mmio_ahb_0_hreadyout(1'b1),
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.mmio_ahb_0_htrans(),
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.mmio_ahb_0_hsize(),
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.mmio_ahb_0_hburst(),
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.mmio_ahb_0_hwrite(),
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.mmio_ahb_0_hprot(),
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.mmio_ahb_0_haddr(),
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.mmio_ahb_0_hwdata(),
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.mmio_ahb_0_hresp(2'b0),
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.mmio_ahb_0_hrdata(32'b0),
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.mmio_ahb_0_hmaster(),
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.mmio_ahb_0_hsplit(16'b0),
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.interrupts(2'b0),
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.cdrio_overCLK(clk400),
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.cdrio_uDatIn(uDatSer[2]),
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.cdrio_uDatOut(uDatSer[1]),
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.cdrio_dDatIn(dDatSer[1]),
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.cdrio_dDatOut(dDatSer[2])
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);
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ExampleRocketSystem s_rocket_slv2(
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.clock(clock),
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.reset(reset),
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.resetctrl_hartIsInReset_0(reset),
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.debug_clock(clock),
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.debug_reset(reset),
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.debug_systemjtag_jtag_TCK(1'b0),
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.debug_systemjtag_jtag_TMS(1'b0),
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.debug_systemjtag_jtag_TDI(1'b0),
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.debug_systemjtag_jtag_TDO_data(),
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.debug_systemjtag_jtag_TDO_driven(),
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.debug_systemjtag_reset(reset),
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.debug_systemjtag_mfr_id(11'b0),
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.debug_systemjtag_part_number(16'b0),
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.debug_systemjtag_version(4'b0),
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.debug_ndreset(),
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.debug_dmactive(dmactive[3]),
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.debug_dmactiveAck(dmactive[3]),
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.mmio_apb_0_psel(),
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.mmio_apb_0_penable(),
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.mmio_apb_0_pwrite(),
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.mmio_apb_0_paddr(),
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.mmio_apb_0_pprot(),
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.mmio_apb_0_pwdata(),
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.mmio_apb_0_pstrb(),
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.mmio_apb_0_pready(1'b1),
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.mmio_apb_0_pslverr(1'b0),
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.mmio_apb_0_prdata(32'b0),
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.mmio_ahb_0_hmastlock(),
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.mmio_ahb_0_hsel(),
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.mmio_ahb_0_hready(),
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.mmio_ahb_0_hreadyout(1'b1),
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.mmio_ahb_0_htrans(),
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.mmio_ahb_0_hsize(),
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.mmio_ahb_0_hburst(),
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.mmio_ahb_0_hwrite(),
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.mmio_ahb_0_hprot(),
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.mmio_ahb_0_haddr(),
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.mmio_ahb_0_hwdata(),
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.mmio_ahb_0_hresp(2'b0),
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.mmio_ahb_0_hrdata(32'b0),
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.mmio_ahb_0_hmaster(),
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.mmio_ahb_0_hsplit(16'b0),
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.interrupts(2'b0),
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.cdrio_overCLK(clk400),
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.cdrio_uDatIn(1'b0),
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.cdrio_uDatOut(uDatSer[2]),
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.cdrio_dDatIn(dDatSer[2]),
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.cdrio_dDatOut()
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);
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*/
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// wire debugger_success;
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// debuger i_debuger(
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// .success(debugger_success),
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// .DEBUGER_AWID (mmio_axi4_0_aw_bits_id),
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// .DEBUGER_BID (mmio_axi4_0_b_bits_id),
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// .DEBUGER_ARID (mmio_axi4_0_ar_bits_id),
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// .DEBUGER_RID (mmio_axi4_0_r_bits_id),
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// .DEBUGER_AWADDR (mmio_axi4_0_aw_bits_addr),
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// .DEBUGER_AWVALID(mmio_axi4_0_aw_valid),
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// .DEBUGER_AWREADY(mmio_axi4_0_aw_ready),
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// .DEBUGER_WDATA (mmio_axi4_0_w_bits_data),
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// .DEBUGER_WSTRB (mmio_axi4_0_w_bits_strb),
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// .DEBUGER_WVALID(mmio_axi4_0_w_valid),
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// .DEBUGER_WREADY(mmio_axi4_0_w_ready),
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// .DEBUGER_BRESP (mmio_axi4_0_b_bits_resp),
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// .DEBUGER_BVALID(mmio_axi4_0_b_valid),
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// .DEBUGER_BREADY(mmio_axi4_0_b_ready),
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// .DEBUGER_ARADDR (mmio_axi4_0_ar_bits_addr),
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// .DEBUGER_ARVALID(mmio_axi4_0_ar_valid),
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// .DEBUGER_ARREADY(mmio_axi4_0_ar_ready),
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// .DEBUGER_RDATA (mmio_axi4_0_r_bits_data),
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// .DEBUGER_RRESP (mmio_axi4_0_r_bits_resp),
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// .DEBUGER_RVALID(mmio_axi4_0_r_valid),
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// .DEBUGER_RREADY(mmio_axi4_0_r_ready),
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// .CLK(CLK),
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// .RSTn(RSTn)
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// );
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// reg [1023:0] firmware_file;
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// initial begin
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// if ($value$plusargs("%s", firmware_file)) begin
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// $display("%s", firmware_file);
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// $readmemh(firmware_file, s_rocket.ram.Mem_SRAM.Mem_SRAM_ext.ram);
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// end
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// end
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// assign success = debugger_success;
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string testName;
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`define MEM0 s_rocket_mst.ram.Mem_SRAM.Mem_SRAM_ext.ram
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`define MEM1 s_rocket_slv0.ram.Mem_SRAM.Mem_SRAM_ext.ram
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`define MEM2 s_rocket_slv1.ram.Mem_SRAM.Mem_SRAM_ext.ram
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`define MEM3 s_rocket_slv2.ram.Mem_SRAM.Mem_SRAM_ext.ram
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reg [7:0] mem0 [0:200000];
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reg [7:0] mem1 [0:200000];
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reg [7:0] mem2 [0:200000];
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reg [7:0] mem3 [0:200000];
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localparam DP = 8192;
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integer i;
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initial begin
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#20
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$readmemh("./tb/sw/build/mstTest.verilog", mem0);
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for ( i = 0; i < DP; i = i + 1 ) begin
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if ( mem0[i*4+0] || mem0[i*4+1] || mem0[i*4+2] || mem0[i*4+3] ) begin
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`MEM0[i] = {mem0[i*4+3], mem0[i*4+2], mem0[i*4+1], mem0[i*4+0]};
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end
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else begin
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`MEM0[i] = 32'h0;
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end
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// $display("MEM0[%d] = %h", i, `MEM0[i]);
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end
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// $readmemh("./tb/sw/build/slvTest.verilog", mem1);
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// for ( i = 0; i < DP; i = i + 1 ) begin
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// if ( mem1[i*4+0] || mem1[i*4+1] || mem1[i*4+2] || mem1[i*4+3] ) begin
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// `MEM1[i] = {mem1[i*4+3], mem1[i*4+2], mem1[i*4+1], mem1[i*4+0]};
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// end
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// else begin
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// `MEM1[i] = 32'h0;
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// end
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// end
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// $readmemh("./tb/sw/build/slvTest.verilog", mem2);
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// for ( i = 0; i < DP; i = i + 1 ) begin
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// if ( mem2[i*4+0] || mem2[i*4+1] || mem2[i*4+2] || mem2[i*4+3] ) begin
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// `MEM2[i] = {mem2[i*4+3], mem2[i*4+2], mem2[i*4+1], mem2[i*4+0]};
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// end
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// else begin
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// `MEM2[i] = 32'h0;
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// end
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// end
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// $readmemh("./tb/sw/build/slvTest.verilog", mem3);
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// for ( i = 0; i < DP; i = i + 1 ) begin
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// if ( mem3[i*4+0] || mem3[i*4+1] || mem3[i*4+2] || mem3[i*4+3] ) begin
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// `MEM3[i] = {mem3[i*4+3], mem3[i*4+2], mem3[i*4+1], mem3[i*4+0]};
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// end
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// else begin
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// `MEM3[i] = 32'h0;
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// end
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// end
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end
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endmodule
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