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This commit is contained in:
Ruige Lee
2025-01-15 17:58:12 +08:00
parent 8236d45154
commit f63e3a831b
5 changed files with 173 additions and 66 deletions
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68
tb/verilator/SimTop.v
View File

@@ -84,7 +84,7 @@ ExampleRocketSystem s_rocket_mst(
.cdrio_dDatOut(dDatSer[0])
);
/*
ExampleRocketSystem s_rocket_slv0(
.clock(clock),
.reset(reset),
@@ -254,7 +254,7 @@ ExampleRocketSystem s_rocket_slv2(
.cdrio_dDatIn(dDatSer[2]),
.cdrio_dDatOut()
);
*/
@@ -337,14 +337,6 @@ integer i;
initial begin
#20
// if ( $value$plusargs("%s",testName) ) begin
// $display("%s",testName);
// $readmemh(testName, mem);
// end
// else begin
// $display("%s",testName);
// $error("Failed to read Files!");
// end
$readmemh("./tb/sw/build/mstTest.verilog", mem0);
for ( i = 0; i < DP; i = i + 1 ) begin
@@ -355,38 +347,38 @@ initial begin
`MEM0[i] = 32'h0;
end
$display("%x",`MEM0[i]);
// $display("MEM0[%d] = %h", i, `MEM0[i]);
end
$readmemh("./tb/sw/build/slvTest.verilog", mem1);
for ( i = 0; i < DP; i = i + 1 ) begin
if ( mem1[i*4+0] || mem1[i*4+1] || mem1[i*4+2] || mem1[i*4+3] ) begin
`MEM1[i] = {mem1[i*4+3], mem1[i*4+2], mem1[i*4+1], mem1[i*4+0]};
end
else begin
`MEM1[i] = 32'h0;
end
end
// $readmemh("./tb/sw/build/slvTest.verilog", mem1);
// for ( i = 0; i < DP; i = i + 1 ) begin
// if ( mem1[i*4+0] || mem1[i*4+1] || mem1[i*4+2] || mem1[i*4+3] ) begin
// `MEM1[i] = {mem1[i*4+3], mem1[i*4+2], mem1[i*4+1], mem1[i*4+0]};
// end
// else begin
// `MEM1[i] = 32'h0;
// end
// end
$readmemh("./tb/sw/build/slvTest.verilog", mem2);
for ( i = 0; i < DP; i = i + 1 ) begin
if ( mem2[i*4+0] || mem2[i*4+1] || mem2[i*4+2] || mem2[i*4+3] ) begin
`MEM2[i] = {mem2[i*4+3], mem2[i*4+2], mem2[i*4+1], mem2[i*4+0]};
end
else begin
`MEM2[i] = 32'h0;
end
end
// $readmemh("./tb/sw/build/slvTest.verilog", mem2);
// for ( i = 0; i < DP; i = i + 1 ) begin
// if ( mem2[i*4+0] || mem2[i*4+1] || mem2[i*4+2] || mem2[i*4+3] ) begin
// `MEM2[i] = {mem2[i*4+3], mem2[i*4+2], mem2[i*4+1], mem2[i*4+0]};
// end
// else begin
// `MEM2[i] = 32'h0;
// end
// end
$readmemh("./tb/sw/build/slvTest.verilog", mem3);
for ( i = 0; i < DP; i = i + 1 ) begin
if ( mem3[i*4+0] || mem3[i*4+1] || mem3[i*4+2] || mem3[i*4+3] ) begin
`MEM3[i] = {mem3[i*4+3], mem3[i*4+2], mem3[i*4+1], mem3[i*4+0]};
end
else begin
`MEM3[i] = 32'h0;
end
end
// $readmemh("./tb/sw/build/slvTest.verilog", mem3);
// for ( i = 0; i < DP; i = i + 1 ) begin
// if ( mem3[i*4+0] || mem3[i*4+1] || mem3[i*4+2] || mem3[i*4+3] ) begin
// `MEM3[i] = {mem3[i*4+3], mem3[i*4+2], mem3[i*4+1], mem3[i*4+0]};
// end
// else begin
// `MEM3[i] = 32'h0;
// end
// end
end

2
tb/verilator/sim_main.cpp
View File

@@ -140,7 +140,7 @@ int main(int argc, char **argv, char **env) {
#endif
if ( flag_limitEnable ) {
if ( main_cycle > 3000 ){
if ( main_cycle > 30000 ){
std::cout << "Timeout!!!!!" << std::endl;
sim_exit();
return -1;