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实现统计寄存器组

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This commit is contained in:
Ruige Lee
2025-07-29 11:56:10 +08:00
parent 1791a54dae
commit f630310582
5 changed files with 264 additions and 1 deletions
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221
src/main/scala/backBoard/shin/Interface.scala
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@@ -4,6 +4,22 @@ import chisel3._
import chisel3.util._
class Stat_IO_Bundle extends Bundle{
val isHeaderError = Bool()
val isSubHeaderError = Bool()
val isPayloadError = Bool()
val isSubTailError = Bool()
val isCRCError = Bool()
val isFinish = Bool()
val isRecByteAck = Bool()
def isRecError = isHeaderError | isSubHeaderError | isPayloadError | isSubTailError | isCRCError
}
class EBMMU_Bundle extends Bundle{
val lAddr = UInt(30.W)
val pAddr = UInt(16.W)
@@ -44,6 +60,25 @@ class CommonRegisterBundle extends Bundle{
// val recByteCnt = UInt(32.W)
// val forwardByteCnt = UInt(32.W)
val statDownRecErrorCnt = UInt(32.W)
val statDownRecHeaderErrorCnt = UInt(16.W)
val statDownRecSubHeaderErrorCnt = UInt(16.W)
val statDownRecPayloadErrorCnt = UInt(16.W)
val statDownRecSubTailErrorCnt = UInt(16.W)
val statDownRecCRCErrorCnt = UInt(16.W)
val statDownRecFinishCnt = UInt(32.W)
val statDownRecByteCnt = UInt(64.W)
val statUpRecErrorCnt = UInt(32.W)
val statUpRecHeaderErrorCnt = UInt(16.W)
val statUpRecSubHeaderErrorCnt = UInt(16.W)
val statUpRecPayloadErrorCnt = UInt(16.W)
val statUpRecSubTailErrorCnt = UInt(16.W)
val statUpRecCRCErrorCnt = UInt(16.W)
val statUpRecFinishCnt = UInt(32.W)
val statUpRecByteCnt = UInt(64.W)
val wdtStatus = UInt(32.W)
@@ -183,6 +218,9 @@ class InterfaceIO extends Bundle{
val interrupt = Output(Bool())
val wdtTrigger = Input(Vec(17, Bool()))
val downRecStat = Input(new Stat_IO_Bundle)
val upRecStat = Input(new Stat_IO_Bundle)
}
@@ -275,6 +313,60 @@ abstract class InterfaceBase extends Module{
(addr === "h7d".U ) -> cReg.intMode(15,8),
(addr === "h80".U ) -> cReg.statDownRecErrorCnt(7,0),
(addr === "h81".U ) -> cReg.statDownRecErrorCnt(15,8),
(addr === "h82".U ) -> cReg.statDownRecHeaderErrorCnt(7,0),
(addr === "h83".U ) -> cReg.statDownRecHeaderErrorCnt(15,8),
(addr === "h84".U ) -> cReg.statDownRecSubHeaderErrorCnt(7,0),
(addr === "h85".U ) -> cReg.statDownRecSubHeaderErrorCnt(15,8),
(addr === "h86".U ) -> cReg.statDownRecPayloadErrorCnt(7,0),
(addr === "h87".U ) -> cReg.statDownRecPayloadErrorCnt(15,8),
(addr === "h88".U ) -> cReg.statDownRecSubTailErrorCnt(7,0),
(addr === "h89".U ) -> cReg.statDownRecSubTailErrorCnt(15,8),
(addr === "h8a".U ) -> cReg.statDownRecCRCErrorCnt(7,0),
(addr === "h8b".U ) -> cReg.statDownRecCRCErrorCnt(15,8),
(addr === "h8c".U ) -> cReg.statDownRecFinishCnt(7,0),
(addr === "h8d".U ) -> cReg.statDownRecFinishCnt(15,8),
(addr === "h8e".U ) -> cReg.statDownRecFinishCnt(23,16),
(addr === "h8f".U ) -> cReg.statDownRecFinishCnt(31,24),
(addr === "h90".U ) -> cReg.statDownRecByteCnt(7,0),
(addr === "h91".U ) -> cReg.statDownRecByteCnt(15,8),
(addr === "h92".U ) -> cReg.statDownRecByteCnt(23,16),
(addr === "h93".U ) -> cReg.statDownRecByteCnt(31,24),
(addr === "h94".U ) -> cReg.statDownRecByteCnt(39,32),
(addr === "h95".U ) -> cReg.statDownRecByteCnt(47,40),
(addr === "h96".U ) -> cReg.statDownRecByteCnt(55,48),
(addr === "h97".U ) -> cReg.statDownRecByteCnt(63,56),
(addr === "ha0".U ) -> cReg.statUpRecErrorCnt(7,0),
(addr === "ha1".U ) -> cReg.statUpRecErrorCnt(15,8),
(addr === "ha2".U ) -> cReg.statUpRecHeaderErrorCnt(7,0),
(addr === "ha3".U ) -> cReg.statUpRecHeaderErrorCnt(15,8),
(addr === "ha4".U ) -> cReg.statUpRecSubHeaderErrorCnt(7,0),
(addr === "ha5".U ) -> cReg.statUpRecSubHeaderErrorCnt(15,8),
(addr === "ha6".U ) -> cReg.statUpRecPayloadErrorCnt(7,0),
(addr === "ha7".U ) -> cReg.statUpRecPayloadErrorCnt(15,8),
(addr === "ha8".U ) -> cReg.statUpRecSubTailErrorCnt(7,0),
(addr === "ha9".U ) -> cReg.statUpRecSubTailErrorCnt(15,8),
(addr === "haa".U ) -> cReg.statUpRecCRCErrorCnt(7,0),
(addr === "hab".U ) -> cReg.statUpRecCRCErrorCnt(15,8),
(addr === "hac".U ) -> cReg.statUpRecFinishCnt(7,0),
(addr === "had".U ) -> cReg.statUpRecFinishCnt(15,8),
(addr === "hae".U ) -> cReg.statUpRecFinishCnt(23,16),
(addr === "haf".U ) -> cReg.statUpRecFinishCnt(31,24),
(addr === "hb0".U ) -> cReg.statUpRecByteCnt(7,0),
(addr === "hb1".U ) -> cReg.statUpRecByteCnt(15,8),
(addr === "hb2".U ) -> cReg.statUpRecByteCnt(23,16),
(addr === "hb3".U ) -> cReg.statUpRecByteCnt(31,24),
(addr === "hb4".U ) -> cReg.statUpRecByteCnt(39,32),
(addr === "hb5".U ) -> cReg.statUpRecByteCnt(47,40),
(addr === "hb6".U ) -> cReg.statUpRecByteCnt(55,48),
(addr === "hb7".U ) -> cReg.statUpRecByteCnt(63,56),
(addr === "hc0".U ) -> Cat( sReg.isDevOnRightModify, sReg.isDevOnRight, 0.U(3.W) ),
(addr === "hc2".U ) -> sReg.indexOfRightDev(7,0),
(addr === "hc3".U ) -> sReg.indexOfRightDev(13,8),
@@ -958,11 +1050,140 @@ trait InterfaceSystem{ this: InterfaceBase =>
}
trait InterfaceStat{ this: InterfaceBase =>
val statDownRecErrorCnt = RegInit(0.U(32.W)); cReg.statDownRecErrorCnt := statDownRecErrorCnt
val statDownRecHeaderErrorCnt = RegInit(0.U(16.W)); cReg.statDownRecHeaderErrorCnt := statDownRecHeaderErrorCnt
val statDownRecSubHeaderErrorCnt = RegInit(0.U(16.W)); cReg.statDownRecSubHeaderErrorCnt := statDownRecSubHeaderErrorCnt
val statDownRecPayloadErrorCnt = RegInit(0.U(16.W)); cReg.statDownRecPayloadErrorCnt := statDownRecPayloadErrorCnt
val statDownRecSubTailErrorCnt = RegInit(0.U(16.W)); cReg.statDownRecSubTailErrorCnt := statDownRecSubTailErrorCnt
val statDownRecCRCErrorCnt = RegInit(0.U(16.W)); cReg.statDownRecCRCErrorCnt := statDownRecCRCErrorCnt
val statDownRecFinishCnt = RegInit(0.U(32.W)); cReg.statDownRecFinishCnt := statDownRecFinishCnt
val statDownRecByteCnt = RegInit(0.U(64.W)); cReg.statDownRecByteCnt := statDownRecByteCnt
val statUpRecErrorCnt = RegInit(0.U(32.W)); cReg.statUpRecErrorCnt := statUpRecErrorCnt
val statUpRecHeaderErrorCnt = RegInit(0.U(16.W)); cReg.statUpRecHeaderErrorCnt := statUpRecHeaderErrorCnt
val statUpRecSubHeaderErrorCnt = RegInit(0.U(16.W)); cReg.statUpRecSubHeaderErrorCnt := statUpRecSubHeaderErrorCnt
val statUpRecPayloadErrorCnt = RegInit(0.U(16.W)); cReg.statUpRecPayloadErrorCnt := statUpRecPayloadErrorCnt
val statUpRecSubTailErrorCnt = RegInit(0.U(16.W)); cReg.statUpRecSubTailErrorCnt := statUpRecSubTailErrorCnt
val statUpRecCRCErrorCnt = RegInit(0.U(16.W)); cReg.statUpRecCRCErrorCnt := statUpRecCRCErrorCnt
val statUpRecFinishCnt = RegInit(0.U(32.W)); cReg.statUpRecFinishCnt := statUpRecFinishCnt
val statUpRecByteCnt = RegInit(0.U(64.W)); cReg.statUpRecByteCnt := statUpRecByteCnt
when(io.lvds.isEnW & (io.lvds.addrw === "h80".U )){
statDownRecErrorCnt := 0.U
} .elsewhen( io.downRecStat.isRecError ){
statDownRecErrorCnt := statDownRecErrorCnt + 1.U
}
when(io.lvds.isEnW & (io.lvds.addrw === "h82".U )){
statDownRecHeaderErrorCnt := 0.U
} .elsewhen( io.downRecStat.isHeaderError ){
statDownRecHeaderErrorCnt := statDownRecHeaderErrorCnt + 1.U
}
when(io.lvds.isEnW & (io.lvds.addrw === "h84".U )){
statDownRecSubHeaderErrorCnt := 0.U
} .elsewhen( io.downRecStat.isSubHeaderError ){
statDownRecSubHeaderErrorCnt := statDownRecSubHeaderErrorCnt + 1.U
}
when(io.lvds.isEnW & (io.lvds.addrw === "h86".U )){
statDownRecPayloadErrorCnt := 0.U
} .elsewhen( io.downRecStat.isPayloadError ){
statDownRecPayloadErrorCnt := statDownRecPayloadErrorCnt + 1.U
}
when(io.lvds.isEnW & (io.lvds.addrw === "h88".U )){
statDownRecSubTailErrorCnt := 0.U
} .elsewhen( io.downRecStat.isSubTailError ){
statDownRecSubTailErrorCnt := statDownRecSubTailErrorCnt + 1.U
}
when(io.lvds.isEnW & (io.lvds.addrw === "h8a".U )){
statDownRecCRCErrorCnt := 0.U
} .elsewhen( io.downRecStat.isCRCError ){
statDownRecCRCErrorCnt := statDownRecCRCErrorCnt + 1.U
}
when(io.lvds.isEnW & (io.lvds.addrw === "h8c".U )){
statDownRecFinishCnt := 0.U
} .elsewhen( io.downRecStat.isFinish ){
statDownRecFinishCnt := statDownRecFinishCnt + 1.U
}
when(io.lvds.isEnW & (io.lvds.addrw === "h90".U )){
statDownRecByteCnt := 0.U
} .elsewhen( io.downRecStat.isRecByteAck ){
statDownRecByteCnt := statDownRecByteCnt + 1.U
}
when(io.lvds.isEnW & (io.lvds.addrw === "ha0".U )){
statUpRecErrorCnt := 0.U
} .elsewhen( io.upRecStat.isRecError ){
statUpRecErrorCnt := statUpRecErrorCnt + 1.U
}
when(io.lvds.isEnW & (io.lvds.addrw === "ha2".U )){
statUpRecHeaderErrorCnt := 0.U
} .elsewhen( io.upRecStat.isHeaderError ){
statUpRecHeaderErrorCnt := statUpRecHeaderErrorCnt + 1.U
}
when(io.lvds.isEnW & (io.lvds.addrw === "ha4".U )){
statUpRecSubHeaderErrorCnt := 0.U
} .elsewhen( io.upRecStat.isSubHeaderError ){
statUpRecSubHeaderErrorCnt := statUpRecSubHeaderErrorCnt + 1.U
}
when(io.lvds.isEnW & (io.lvds.addrw === "ha6".U )){
statUpRecPayloadErrorCnt := 0.U
} .elsewhen( io.upRecStat.isPayloadError ){
statUpRecPayloadErrorCnt := statUpRecPayloadErrorCnt + 1.U
}
when(io.lvds.isEnW & (io.lvds.addrw === "ha8".U )){
statUpRecSubTailErrorCnt := 0.U
} .elsewhen( io.upRecStat.isSubTailError ){
statUpRecSubTailErrorCnt := statUpRecSubTailErrorCnt + 1.U
}
when(io.lvds.isEnW & (io.lvds.addrw === "haa".U )){
statUpRecCRCErrorCnt := 0.U
} .elsewhen( io.upRecStat.isCRCError ){
statUpRecCRCErrorCnt := statUpRecCRCErrorCnt + 1.U
}
when(io.lvds.isEnW & (io.lvds.addrw === "hac".U )){
statUpRecFinishCnt := 0.U
} .elsewhen( io.upRecStat.isFinish ){
statUpRecFinishCnt := statUpRecFinishCnt + 1.U
}
when(io.lvds.isEnW & (io.lvds.addrw === "hb0".U )){
statUpRecByteCnt := 0.U
} .elsewhen( io.upRecStat.isRecByteAck ){
statUpRecByteCnt := statUpRecByteCnt + 1.U
}
}
class Interface extends InterfaceBase
with InterfaceMCUop
with InterfaceCheckSM
with InterfaceLVDSop
with InterfaceSync
with InterfaceStat
// with InterfaceWdt
with InterfaceSystem
{