diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index bdbe97e..02429e7 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -4,6 +4,22 @@ import chisel3._
 import chisel3.util._
 
 
+
+
+class Stat_IO_Bundle extends Bundle{
+  val isHeaderError    = Bool()
+  val isSubHeaderError = Bool()
+  val isPayloadError   = Bool()
+  val isSubTailError   = Bool()
+  val isCRCError       = Bool()
+  val isFinish         = Bool()
+  val isRecByteAck     = Bool()
+
+  def isRecError = isHeaderError | isSubHeaderError | isPayloadError | isSubTailError | isCRCError
+}
+
+
+
 class EBMMU_Bundle extends Bundle{
   val lAddr = UInt(30.W)
   val pAddr = UInt(16.W)
@@ -44,6 +60,25 @@ class CommonRegisterBundle extends Bundle{
   // val recByteCnt     = UInt(32.W)
   // val forwardByteCnt = UInt(32.W)
 
+  val statDownRecErrorCnt          = UInt(32.W)
+  val statDownRecHeaderErrorCnt    = UInt(16.W)
+  val statDownRecSubHeaderErrorCnt = UInt(16.W)
+  val statDownRecPayloadErrorCnt   = UInt(16.W)
+  val statDownRecSubTailErrorCnt   = UInt(16.W)
+  val statDownRecCRCErrorCnt       = UInt(16.W)
+  val statDownRecFinishCnt         = UInt(32.W)
+  val statDownRecByteCnt           = UInt(64.W)
+
+  val statUpRecErrorCnt          = UInt(32.W)
+  val statUpRecHeaderErrorCnt    = UInt(16.W)
+  val statUpRecSubHeaderErrorCnt = UInt(16.W)
+  val statUpRecPayloadErrorCnt   = UInt(16.W)
+  val statUpRecSubTailErrorCnt   = UInt(16.W)
+  val statUpRecCRCErrorCnt       = UInt(16.W)
+  val statUpRecFinishCnt         = UInt(32.W)
+  val statUpRecByteCnt           = UInt(64.W)
+
+
 
 
   val wdtStatus = UInt(32.W)
@@ -183,6 +218,9 @@ class InterfaceIO extends Bundle{
   val interrupt = Output(Bool())
 
   val wdtTrigger = Input(Vec(17, Bool()))
+
+  val downRecStat = Input(new Stat_IO_Bundle)
+  val upRecStat   = Input(new Stat_IO_Bundle)
 }
 
 
@@ -275,6 +313,60 @@ abstract class InterfaceBase extends Module{
         (addr === "h7d".U ) -> cReg.intMode(15,8),
 
 
+        (addr === "h80".U ) -> cReg.statDownRecErrorCnt(7,0),
+        (addr === "h81".U ) -> cReg.statDownRecErrorCnt(15,8),
+        (addr === "h82".U ) -> cReg.statDownRecHeaderErrorCnt(7,0),
+        (addr === "h83".U ) -> cReg.statDownRecHeaderErrorCnt(15,8),
+        (addr === "h84".U ) -> cReg.statDownRecSubHeaderErrorCnt(7,0),
+        (addr === "h85".U ) -> cReg.statDownRecSubHeaderErrorCnt(15,8),
+        (addr === "h86".U ) -> cReg.statDownRecPayloadErrorCnt(7,0),
+        (addr === "h87".U ) -> cReg.statDownRecPayloadErrorCnt(15,8),
+        (addr === "h88".U ) -> cReg.statDownRecSubTailErrorCnt(7,0),
+        (addr === "h89".U ) -> cReg.statDownRecSubTailErrorCnt(15,8),
+        (addr === "h8a".U ) -> cReg.statDownRecCRCErrorCnt(7,0),
+        (addr === "h8b".U ) -> cReg.statDownRecCRCErrorCnt(15,8),
+        (addr === "h8c".U ) -> cReg.statDownRecFinishCnt(7,0),
+        (addr === "h8d".U ) -> cReg.statDownRecFinishCnt(15,8),
+        (addr === "h8e".U ) -> cReg.statDownRecFinishCnt(23,16),
+        (addr === "h8f".U ) -> cReg.statDownRecFinishCnt(31,24),
+        (addr === "h90".U ) -> cReg.statDownRecByteCnt(7,0),
+        (addr === "h91".U ) -> cReg.statDownRecByteCnt(15,8),
+        (addr === "h92".U ) -> cReg.statDownRecByteCnt(23,16),
+        (addr === "h93".U ) -> cReg.statDownRecByteCnt(31,24),
+        (addr === "h94".U ) -> cReg.statDownRecByteCnt(39,32),
+        (addr === "h95".U ) -> cReg.statDownRecByteCnt(47,40),
+        (addr === "h96".U ) -> cReg.statDownRecByteCnt(55,48),
+        (addr === "h97".U ) -> cReg.statDownRecByteCnt(63,56),
+
+
+        (addr === "ha0".U ) -> cReg.statUpRecErrorCnt(7,0),
+        (addr === "ha1".U ) -> cReg.statUpRecErrorCnt(15,8),
+        (addr === "ha2".U ) -> cReg.statUpRecHeaderErrorCnt(7,0),
+        (addr === "ha3".U ) -> cReg.statUpRecHeaderErrorCnt(15,8),
+        (addr === "ha4".U ) -> cReg.statUpRecSubHeaderErrorCnt(7,0),
+        (addr === "ha5".U ) -> cReg.statUpRecSubHeaderErrorCnt(15,8),
+        (addr === "ha6".U ) -> cReg.statUpRecPayloadErrorCnt(7,0),
+        (addr === "ha7".U ) -> cReg.statUpRecPayloadErrorCnt(15,8),
+        (addr === "ha8".U ) -> cReg.statUpRecSubTailErrorCnt(7,0),
+        (addr === "ha9".U ) -> cReg.statUpRecSubTailErrorCnt(15,8),
+        (addr === "haa".U ) -> cReg.statUpRecCRCErrorCnt(7,0),
+        (addr === "hab".U ) -> cReg.statUpRecCRCErrorCnt(15,8),
+        (addr === "hac".U ) -> cReg.statUpRecFinishCnt(7,0),
+        (addr === "had".U ) -> cReg.statUpRecFinishCnt(15,8),
+        (addr === "hae".U ) -> cReg.statUpRecFinishCnt(23,16),
+        (addr === "haf".U ) -> cReg.statUpRecFinishCnt(31,24),
+        (addr === "hb0".U ) -> cReg.statUpRecByteCnt(7,0),
+        (addr === "hb1".U ) -> cReg.statUpRecByteCnt(15,8),
+        (addr === "hb2".U ) -> cReg.statUpRecByteCnt(23,16),
+        (addr === "hb3".U ) -> cReg.statUpRecByteCnt(31,24),
+        (addr === "hb4".U ) -> cReg.statUpRecByteCnt(39,32),
+        (addr === "hb5".U ) -> cReg.statUpRecByteCnt(47,40),
+        (addr === "hb6".U ) -> cReg.statUpRecByteCnt(55,48),
+        (addr === "hb7".U ) -> cReg.statUpRecByteCnt(63,56),
+
+
+
+
         (addr === "hc0".U ) -> Cat( sReg.isDevOnRightModify, sReg.isDevOnRight, 0.U(3.W) ),
         (addr === "hc2".U ) -> sReg.indexOfRightDev(7,0),
         (addr === "hc3".U ) -> sReg.indexOfRightDev(13,8),
@@ -958,11 +1050,140 @@ trait InterfaceSystem{ this: InterfaceBase =>
 
 }
 
+trait InterfaceStat{ this: InterfaceBase =>
+
+  val statDownRecErrorCnt          = RegInit(0.U(32.W)); cReg.statDownRecErrorCnt          := statDownRecErrorCnt
+  val statDownRecHeaderErrorCnt    = RegInit(0.U(16.W)); cReg.statDownRecHeaderErrorCnt    := statDownRecHeaderErrorCnt
+  val statDownRecSubHeaderErrorCnt = RegInit(0.U(16.W)); cReg.statDownRecSubHeaderErrorCnt := statDownRecSubHeaderErrorCnt
+  val statDownRecPayloadErrorCnt   = RegInit(0.U(16.W)); cReg.statDownRecPayloadErrorCnt   := statDownRecPayloadErrorCnt
+  val statDownRecSubTailErrorCnt   = RegInit(0.U(16.W)); cReg.statDownRecSubTailErrorCnt   := statDownRecSubTailErrorCnt
+  val statDownRecCRCErrorCnt       = RegInit(0.U(16.W)); cReg.statDownRecCRCErrorCnt       := statDownRecCRCErrorCnt
+  val statDownRecFinishCnt         = RegInit(0.U(32.W)); cReg.statDownRecFinishCnt         := statDownRecFinishCnt
+  val statDownRecByteCnt           = RegInit(0.U(64.W)); cReg.statDownRecByteCnt           := statDownRecByteCnt
+
+  val statUpRecErrorCnt          = RegInit(0.U(32.W)); cReg.statUpRecErrorCnt          := statUpRecErrorCnt
+  val statUpRecHeaderErrorCnt    = RegInit(0.U(16.W)); cReg.statUpRecHeaderErrorCnt    := statUpRecHeaderErrorCnt
+  val statUpRecSubHeaderErrorCnt = RegInit(0.U(16.W)); cReg.statUpRecSubHeaderErrorCnt := statUpRecSubHeaderErrorCnt
+  val statUpRecPayloadErrorCnt   = RegInit(0.U(16.W)); cReg.statUpRecPayloadErrorCnt   := statUpRecPayloadErrorCnt
+  val statUpRecSubTailErrorCnt   = RegInit(0.U(16.W)); cReg.statUpRecSubTailErrorCnt   := statUpRecSubTailErrorCnt
+  val statUpRecCRCErrorCnt       = RegInit(0.U(16.W)); cReg.statUpRecCRCErrorCnt       := statUpRecCRCErrorCnt
+  val statUpRecFinishCnt         = RegInit(0.U(32.W)); cReg.statUpRecFinishCnt         := statUpRecFinishCnt
+  val statUpRecByteCnt           = RegInit(0.U(64.W)); cReg.statUpRecByteCnt           := statUpRecByteCnt
+
+
+
+  when(io.lvds.isEnW & (io.lvds.addrw === "h80".U )){
+    statDownRecErrorCnt := 0.U
+  } .elsewhen( io.downRecStat.isRecError ){
+    statDownRecErrorCnt := statDownRecErrorCnt + 1.U
+  }
+
+  when(io.lvds.isEnW & (io.lvds.addrw === "h82".U )){
+    statDownRecHeaderErrorCnt := 0.U
+  } .elsewhen( io.downRecStat.isHeaderError ){
+    statDownRecHeaderErrorCnt := statDownRecHeaderErrorCnt + 1.U
+  }
+
+  when(io.lvds.isEnW & (io.lvds.addrw === "h84".U )){
+    statDownRecSubHeaderErrorCnt := 0.U
+  } .elsewhen( io.downRecStat.isSubHeaderError ){
+    statDownRecSubHeaderErrorCnt := statDownRecSubHeaderErrorCnt + 1.U
+  }
+
+  when(io.lvds.isEnW & (io.lvds.addrw === "h86".U )){
+    statDownRecPayloadErrorCnt := 0.U
+  } .elsewhen( io.downRecStat.isPayloadError ){
+    statDownRecPayloadErrorCnt := statDownRecPayloadErrorCnt + 1.U
+  }
+
+  when(io.lvds.isEnW & (io.lvds.addrw === "h88".U )){
+    statDownRecSubTailErrorCnt := 0.U
+  } .elsewhen( io.downRecStat.isSubTailError ){
+    statDownRecSubTailErrorCnt := statDownRecSubTailErrorCnt + 1.U
+  }
+
+  when(io.lvds.isEnW & (io.lvds.addrw === "h8a".U )){
+    statDownRecCRCErrorCnt := 0.U
+  } .elsewhen( io.downRecStat.isCRCError ){
+    statDownRecCRCErrorCnt := statDownRecCRCErrorCnt + 1.U
+  }
+
+  when(io.lvds.isEnW & (io.lvds.addrw === "h8c".U )){
+    statDownRecFinishCnt := 0.U
+  } .elsewhen( io.downRecStat.isFinish ){
+    statDownRecFinishCnt := statDownRecFinishCnt + 1.U
+  }
+
+  when(io.lvds.isEnW & (io.lvds.addrw === "h90".U )){
+    statDownRecByteCnt := 0.U
+  } .elsewhen( io.downRecStat.isRecByteAck ){
+    statDownRecByteCnt := statDownRecByteCnt + 1.U
+  }
+
+
+
+
+
+
+  when(io.lvds.isEnW & (io.lvds.addrw === "ha0".U )){
+    statUpRecErrorCnt := 0.U
+  } .elsewhen( io.upRecStat.isRecError ){
+    statUpRecErrorCnt := statUpRecErrorCnt + 1.U
+  }
+
+  when(io.lvds.isEnW & (io.lvds.addrw === "ha2".U )){
+    statUpRecHeaderErrorCnt := 0.U
+  } .elsewhen( io.upRecStat.isHeaderError ){
+    statUpRecHeaderErrorCnt := statUpRecHeaderErrorCnt + 1.U
+  }
+
+  when(io.lvds.isEnW & (io.lvds.addrw === "ha4".U )){
+    statUpRecSubHeaderErrorCnt := 0.U
+  } .elsewhen( io.upRecStat.isSubHeaderError ){
+    statUpRecSubHeaderErrorCnt := statUpRecSubHeaderErrorCnt + 1.U
+  }
+
+  when(io.lvds.isEnW & (io.lvds.addrw === "ha6".U )){
+    statUpRecPayloadErrorCnt := 0.U
+  } .elsewhen( io.upRecStat.isPayloadError ){
+    statUpRecPayloadErrorCnt := statUpRecPayloadErrorCnt + 1.U
+  }
+
+  when(io.lvds.isEnW & (io.lvds.addrw === "ha8".U )){
+    statUpRecSubTailErrorCnt := 0.U
+  } .elsewhen( io.upRecStat.isSubTailError ){
+    statUpRecSubTailErrorCnt := statUpRecSubTailErrorCnt + 1.U
+  }
+
+  when(io.lvds.isEnW & (io.lvds.addrw === "haa".U )){
+    statUpRecCRCErrorCnt := 0.U
+  } .elsewhen( io.upRecStat.isCRCError ){
+    statUpRecCRCErrorCnt := statUpRecCRCErrorCnt + 1.U
+  }
+
+  when(io.lvds.isEnW & (io.lvds.addrw === "hac".U )){
+    statUpRecFinishCnt := 0.U
+  } .elsewhen( io.upRecStat.isFinish ){
+    statUpRecFinishCnt := statUpRecFinishCnt + 1.U
+  }
+
+  when(io.lvds.isEnW & (io.lvds.addrw === "hb0".U )){
+    statUpRecByteCnt := 0.U
+  } .elsewhen( io.upRecStat.isRecByteAck ){
+    statUpRecByteCnt := statUpRecByteCnt + 1.U
+  }
+
+
+}
+
+
+
 class Interface extends InterfaceBase
 with InterfaceMCUop
 with InterfaceCheckSM
 with InterfaceLVDSop
 with InterfaceSync
+with InterfaceStat
 // with InterfaceWdt
 with InterfaceSystem
 {
diff --git a/src/main/scala/backBoard/shin/MasterParser.scala b/src/main/scala/backBoard/shin/MasterParser.scala
index 6f4fe88..280bd54 100644
--- a/src/main/scala/backBoard/shin/MasterParser.scala
+++ b/src/main/scala/backBoard/shin/MasterParser.scala
@@ -23,6 +23,8 @@ class MasterParserIO extends Bundle{
 
   val deltaTimeStamp = Output(UInt(32.W))
 
+  val upRecStat   = Output(new Stat_IO_Bundle)
+
 }
 
 abstract class MasterParserBase extends Module{
@@ -189,7 +191,20 @@ abstract class MasterParserBase extends Module{
 }
 
 
-class MasterParser extends MasterParserBase{
+trait MasterParserStat{ this: MasterParserBase =>
+  io.upRecStat.isHeaderError    := false.B
+  io.upRecStat.isSubHeaderError := false.B
+  io.upRecStat.isPayloadError   := false.B
+  io.upRecStat.isSubTailError   := false.B
+  io.upRecStat.isCRCError       := io.rsp.valid & io.rsp.bits.isError
+  io.upRecStat.isFinish         := io.rsp.valid & ~io.rsp.bits.isError
+  io.upRecStat.isRecByteAck     := io.upIn.fire
+
+  
+}
+
+class MasterParser extends MasterParserBase
+with MasterParserStat{
   val deltaTimeStamp = Reg(UInt(32.W))
   // dontTouch(deltaTimeStamp)
   io.deltaTimeStamp := deltaTimeStamp
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index 9f210f0..b106547 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -256,6 +256,8 @@ abstract class ShinTopBase extends Module{
     interface.io.intHWTrig(0) := false.B
     interface.io.intHWTrig(1) := false.B
 
+    interface.io.downRecStat := 0.U.asTypeOf(new Stat_IO_Bundle)
+    interface.io.upRecStat   := 0.U.asTypeOf(new Stat_IO_Bundle)
   }
 
 }
@@ -305,6 +307,9 @@ trait ShinTopMaster{ this: ShinTopBase =>
     interface.io.intMstTrig(0) := masterParser.io.txDeq
     interface.io.intMstTrig(1) := masterParser.io.rxEnq
 
+    interface.io.downRecStat := 0.U.asTypeOf(new Stat_IO_Bundle)
+    interface.io.upRecStat   := masterParser.io.upRecStat
+
   }
 
   masterParser.io.req         := interface.io.txReq.valid
@@ -369,6 +374,10 @@ trait ShinTopSlave{ this: ShinTopBase =>
     interface.io.intHWTrig(0) := slaveParser.io.intHWTrig(0)
     interface.io.intHWTrig(1) := slaveParser.io.intHWTrig(1)
 
+
+    interface.io.downRecStat := slaveParser.io.downRecStat
+    interface.io.upRecStat   := slaveParser.io.upRecStat
+
   }
 
   slaveParser.io.intHWClr(0) := interface.io.intHWClr(0)
diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala
index 07768d4..8427204 100644
--- a/src/main/scala/backBoard/shin/SlaveParser.scala
+++ b/src/main/scala/backBoard/shin/SlaveParser.scala
@@ -77,6 +77,9 @@ class SlaveParserIO extends Bundle{
 
   val intHWTrig   = Output(Vec(2, Bool()))
   val intHWClr    = Input (Vec(2, Bool()))
+
+  val downRecStat = Output(new Stat_IO_Bundle)
+  val upRecStat   = Output(new Stat_IO_Bundle)
 }
 
 abstract class SlaveParserBase extends Module{
@@ -1048,6 +1051,9 @@ with SlaveParserProbe{
 
   downRecParser.io.resp := io.intHWClr(0)
   upRecParser.io.resp   := io.intHWClr(1)
+
+  io.downRecStat := downRecParser.io.stat
+  io.upRecStat   := upRecParser.io.stat
 }
 
 
diff --git a/src/main/scala/backBoard/shin/SlaveRecParser.scala b/src/main/scala/backBoard/shin/SlaveRecParser.scala
index 78fbcc9..e340a68 100644
--- a/src/main/scala/backBoard/shin/SlaveRecParser.scala
+++ b/src/main/scala/backBoard/shin/SlaveRecParser.scala
@@ -19,6 +19,8 @@ class SlaveRecParserIO extends Bundle{
   val resp = Input(Bool())
   val isError = Output(Bool())
 
+  val stat = Output(new Stat_IO_Bundle)
+
 
 }
 
@@ -75,6 +77,7 @@ class SlaveRecParser extends Module{
   val frameLenCnt = Reg(UInt(12.W)) //帧长度计数
 
 
+
   io.frameReq.valid := (stateCurr === STATE_HEADER) & (stateNext === STATE_SUBMSG_HEADER | stateNext === STATE_CRC)
   val frameHeader = Reg(new FrameHeader)
   io.frameReq.bits.frameLenAim := frameHeader.frameLenAim
@@ -210,6 +213,15 @@ class SlaveRecParser extends Module{
 
 
 
+
+
+  io.stat.isHeaderError    := stateNext === STATE_ERROR & stateCurr === STATE_HEADER
+  io.stat.isSubHeaderError := stateNext === STATE_ERROR & stateCurr === STATE_SUBMSG_HEADER
+  io.stat.isPayloadError   := stateNext === STATE_ERROR & stateCurr === STATE_PAYLOAD_DATA
+  io.stat.isSubTailError   := stateNext === STATE_ERROR & stateCurr === STATE_SUBMSG_TAIL
+  io.stat.isCRCError       := stateNext === STATE_ERROR & stateCurr === STATE_CRC
+  io.stat.isFinish         := stateNext === STATE_IDLE  & stateCurr === STATE_CRC
+  io.stat.isRecByteAck     := io.rec.fire
 }