添加分频io

src/main/scala/backBoard/shin/MstSlvSwitch.scala

@@ -30,6 +30,7 @@ class TopBase_IO_Bundle extends Bundle{
   val ldo1p1 = Output(UInt(8.W))
   val refTop = Output(UInt(3.W))
   val bias   = Output(UInt(2.W))
+  val div4   = Output(UInt(4.W))
 
   val spiSel  = Output(UInt(2.W))
   val isPllCfg = Output(Bool())
@@ -108,6 +109,7 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{
   io.ldo1p1    := interface.io.cReg.ldo1p1
   io.refTop    := interface.io.cReg.refTop
   io.bias      := interface.io.cReg.bias
+  io.div4      := interface.io.cReg.div4
 
   io.spiSel   := interface.io.cReg.spiSel
   io.isPllCfg := interface.io.isPllCfg