From f42c9044d82c6cced3519beab443686ace7bcaea Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Thu, 11 Sep 2025 15:50:38 +0800
Subject: [PATCH] =?UTF-8?q?=E6=B7=BB=E5=8A=A0=E5=88=86=E9=A2=91io?=
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---
 src/main/scala/backBoard/shin/Interface.scala    | 5 ++++-
 src/main/scala/backBoard/shin/MstSlvSwitch.scala | 2 ++
 src/main/scala/backBoard/shin/ShinTop.scala      | 3 ++-
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index 8d3cec5..c663f75 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -51,6 +51,7 @@ class CommonRegisterBundle extends Bundle{
   val ldo1p1 = UInt(8.W)
   val refTop = UInt(3.W)
   val bias   = UInt(2.W)
+  val div4   = UInt(4.W)
 
   val dwupEx   = Bool()
   val b8b4Sel  = Bool()
@@ -212,7 +213,7 @@ class InterfaceIO extends Bundle{
 
   val hwSerial  = Input(UInt(48.W))
   val uniCode   = Input(UInt(64.W))
-  val isPllCfg = Output(Bool())
+  val isPllCfg  = Output(Bool())
 }
 
 
@@ -295,6 +296,7 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
         (addr === "h52".U ) -> cReg.ldo1p1,
         (addr === "h53".U ) -> cReg.refTop,
         (addr === "h54".U ) -> cReg.bias,
+        (addr === "h55".U ) -> cReg.div4,
 
         (addr === "h70".U ) -> cReg.intEnable(7,0),
         (addr === "h71".U ) -> cReg.intEnable(15,8),
@@ -1289,6 +1291,7 @@ trait InterfaceAnalog{ this: InterfaceBase =>
   cReg.ldo1p1 := RegEnable( dataw, "h87".U(8.W), isEnW & addrw === "h52".U )
   cReg.refTop := RegEnable( dataw, "h0".U(8.W), isEnW & addrw === "h53".U )
   cReg.bias   := RegEnable( dataw, "h0".U(8.W), isEnW & addrw === "h54".U )
+  cReg.div4   := RegEnable( dataw(3,0), "h1".U(4.W), isEnW & addrw === "h55".U )
 
   io.isPllCfg := isEnW & addrw === "h45".U
 }
diff --git a/src/main/scala/backBoard/shin/MstSlvSwitch.scala b/src/main/scala/backBoard/shin/MstSlvSwitch.scala
index a3aabf1..3083f31 100644
--- a/src/main/scala/backBoard/shin/MstSlvSwitch.scala
+++ b/src/main/scala/backBoard/shin/MstSlvSwitch.scala
@@ -30,6 +30,7 @@ class TopBase_IO_Bundle extends Bundle{
   val ldo1p1 = Output(UInt(8.W))
   val refTop = Output(UInt(3.W))
   val bias   = Output(UInt(2.W))
+  val div4   = Output(UInt(4.W))
 
   val spiSel  = Output(UInt(2.W))
   val isPllCfg = Output(Bool())
@@ -108,6 +109,7 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{
   io.ldo1p1    := interface.io.cReg.ldo1p1
   io.refTop    := interface.io.cReg.refTop
   io.bias      := interface.io.cReg.bias
+  io.div4      := interface.io.cReg.div4
 
   io.spiSel   := interface.io.cReg.spiSel
   io.isPllCfg := interface.io.isPllCfg
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index a25b868..a26f442 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -6,7 +6,8 @@ import chisel3.util._
 import chisel3.experimental.dataview._
 
 class ShinTopIO extends TopBase_IO_Bundle{
-  val multiCLK = Input(Vec(16, Bool()))
+  val multiCLK     = Input(Vec(16, Bool()))
+  val multiCLKDiv4 = Input(Vec(4, Bool()))
 }