ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

添加分频io

Browse Source
This commit is contained in:
RuigeLee
2025-09-11 15:50:38 +08:00
parent d6ca17c75d
commit f42c9044d8
3 changed files with 8 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/main/scala/backBoard/shin/Interface.scala
View File

@@ -51,6 +51,7 @@ class CommonRegisterBundle extends Bundle{
val ldo1p1 = UInt(8.W)
val refTop = UInt(3.W)
val bias = UInt(2.W)
val div4 = UInt(4.W)
val dwupEx = Bool()
val b8b4Sel = Bool()
@@ -212,7 +213,7 @@ class InterfaceIO extends Bundle{
val hwSerial = Input(UInt(48.W))
val uniCode = Input(UInt(64.W))
val isPllCfg = Output(Bool())
val isPllCfg = Output(Bool())
}
@@ -295,6 +296,7 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
(addr === "h52".U ) -> cReg.ldo1p1,
(addr === "h53".U ) -> cReg.refTop,
(addr === "h54".U ) -> cReg.bias,
(addr === "h55".U ) -> cReg.div4,
(addr === "h70".U ) -> cReg.intEnable(7,0),
(addr === "h71".U ) -> cReg.intEnable(15,8),
@@ -1289,6 +1291,7 @@ trait InterfaceAnalog{ this: InterfaceBase =>
cReg.ldo1p1 := RegEnable( dataw, "h87".U(8.W), isEnW & addrw === "h52".U )
cReg.refTop := RegEnable( dataw, "h0".U(8.W), isEnW & addrw === "h53".U )
cReg.bias := RegEnable( dataw, "h0".U(8.W), isEnW & addrw === "h54".U )
cReg.div4 := RegEnable( dataw(3,0), "h1".U(4.W), isEnW & addrw === "h55".U )
io.isPllCfg := isEnW & addrw === "h45".U
}