fpga测试顶层 虚拟线模式

src/main/verilog/CDRIn_fpga.v

@@ -0,0 +1,62 @@
+module CDRIn_fpga(
+    input clock,
+    input reset,
+    input overCLK,
+    input serDat,
+
+    output reg [7:0] led
+
+);
+
+
+
+    wire       rx_axis_valid;
+    wire [7:0] rx_axis_bits_tdata;
+    wire       rx_axis_bits_tlast;
+    wire       rx_axis_bits_tuser;
+
+
+
+    CDRIn s_CDRIn(
+        .clock(clock),
+        .reset(reset),
+
+        .io_axis_ready(1'b1),
+        .io_axis_valid(rx_axis_valid),
+        .io_axis_bits_tdata(rx_axis_bits_tdata),
+        .io_axis_bits_tlast(rx_axis_bits_tlast),
+        .io_axis_bits_tuser(rx_axis_bits_tuser),
+
+        .io_serDat(serDat),
+        .io_overCLK(overCLK)
+    );
+
+
+
+    reg [7:0] led_temp;
+    reg [7:0] cnt;
+
+    always @(posedge clock) begin
+        if ( rx_axis_valid & 1'b1 ) begin
+            if ( cnt == 0 ) begin
+                led_temp <= rx_axis_bits_tdata;
+                cnt <= cnt + 1;
+            end
+            if ( rx_axis_bits_tlast ) begin
+                cnt <= 0;
+                if( ~rx_axis_bits_tuser ) begin
+                    led <= led_temp;
+                end
+            end
+        end
+    end
+
+
+
+
+
+
+
+
+
+endmodule

src/main/verilog/CDROne_fpga.v

@@ -0,0 +1,69 @@
+module CDROne_fpga(
+    input clock,
+    input resetn,
+    output [7:0] led
+
+//    output serDat_o_p,
+//    output serDat_o_n,
+
+//    input serDat_i_p,
+//    input serDat_i_n
+
+);
+
+wire serDat_o;
+wire serDat_i;
+wire clk100;
+wire clk400;
+
+
+//   IBUFDS #(
+//      .DIFF_TERM("FALSE"),       // Differential Termination
+//      .IBUF_LOW_PWR("TRUE"),     // Low power="TRUE", Highest performance="FALSE" 
+//      .IOSTANDARD("DEFAULT")     // Specify the input I/O standard
+//   ) IBUFDS_inst (
+//      .O(serDat_i),  // Buffer output
+//      .I(serDat_i_p),  // Diff_p buffer input (connect directly to top-level port)
+//      .IB(serDat_i_n) // Diff_n buffer input (connect directly to top-level port)
+//   );
+
+//   OBUFDS #(
+//      .IOSTANDARD("DEFAULT"), // Specify the output I/O standard
+//      .SLEW("SLOW")           // Specify the output slew rate
+//   ) OBUFDS_inst (
+//      .O(serDat_o_p),     // Diff_p output (connect directly to top-level port)
+//      .OB(serDat_o_n),   // Diff_n output (connect directly to top-level port)
+//      .I(serDat_o)      // Buffer input
+//   );
+
+clk_wiz_0 
+ (
+  // Clock out ports
+  .clk_out1(clk100),
+  .clk_out2(clk400),
+ // Clock in ports
+  .clk_in1(clock)
+ );
+
+
+
+
+CDROut_fpga(
+    .clock(clk100),
+    .reset(~resetn),
+    .serDat(serDat_o)
+);
+
+
+CDRIn_fpga(
+    .clock(clk100),
+    .reset(~resetn),
+    .overCLK(clk400),
+    .serDat(serDat_o),
+//    .serDat(serDat_i),
+    .led(led)
+
+);
+
+
+endmodule

src/main/verilog/CDROut_fpga.v

@@ -0,0 +1,113 @@
+module CDROut_fpga(
+    input clock, // 100MHZ
+    input reset,
+
+    output serDat
+
+
+
+);
+
+    wire      tx_axis_ready;
+
+    reg       tx_axis_valid = 0;
+    reg [7:0] tx_axis_bits_tdata;
+    reg       tx_axis_bits_tlast;
+    reg       tx_axis_bits_tuser;
+
+
+    CDROut s_CDROut(
+        .clock(clock),
+        .reset(reset),
+
+        .io_axis_ready(tx_axis_ready),
+        .io_axis_valid(tx_axis_valid),
+        .io_axis_bits_tdata(tx_axis_bits_tdata),
+        .io_axis_bits_tlast(tx_axis_bits_tlast),
+        .io_axis_bits_tuser(tx_axis_bits_tuser),
+        .io_serDat(serDat)
+        );
+
+
+
+
+    reg [31:0] rtc_cnt;
+    always @(posedge clock) begin
+        if( rtc_cnt > 5000000 ) begin
+            rtc_cnt <= #2 0;
+        end else begin
+            rtc_cnt <= #2 rtc_cnt + 1;
+        end
+    end
+
+
+    reg [7:0] cnt;
+    reg [7:0] led_state;
+
+
+    always @(posedge clock) begin
+        if( rtc_cnt == 0 ) begin
+            cnt <= #2 0;
+            
+            led_state <= 
+                led_state == 8'h1 ? 8'h2 : 
+                led_state == 8'h2 ? 8'h4 : 
+                led_state == 8'h4 ? 8'h8 : 
+                led_state == 8'h8 ? 8'h10 :
+                led_state == 8'h10 ? 8'h20 :
+                led_state == 8'h20 ? 8'h40 :
+                led_state == 8'h40 ? 8'h80 : 8'h1;
+            
+        end else begin
+            if( cnt == 8'd0 ) begin
+                tx_axis_valid      <= #2 1'b1;
+                tx_axis_bits_tlast <= #2 1'b0;
+                tx_axis_bits_tdata <= #2 8'h0;
+                tx_axis_bits_tuser <= #2 1'b0;
+                cnt <= #2 cnt + 8'd1;
+            end else begin
+                if( tx_axis_valid & tx_axis_ready ) begin
+                    if ( tx_axis_bits_tlast ) begin
+                        tx_axis_valid      <= #2 1'b0;
+                        tx_axis_bits_tlast <= #2 1'b0;
+                    end else begin
+                        tx_axis_bits_tuser <= #2 1'b0;
+
+                        if( cnt == 8'd0 ) begin
+                            tx_axis_bits_tdata <= #2 8'h0;
+                        end
+                        
+                        if( cnt == 8'd1 ) begin
+                            tx_axis_bits_tdata <= #2 8'h1;
+                        end
+                                     
+                        if( cnt == 8'd2 ) begin
+                            tx_axis_bits_tdata <= #2 8'h0;
+                        end
+
+                        if( cnt == 8'd3 ) begin
+                            tx_axis_bits_tdata <= #2 8'h0;
+                        end
+                        
+                         if( cnt == 8'd4 ) begin
+                            tx_axis_bits_tdata <= #2 led_state;
+                        end
+                                                       
+                        if( cnt == 8'd4 ) begin
+                            tx_axis_bits_tlast <= #2 1'b1;
+                        end else begin
+                            cnt <= #2 cnt + 8'd1;
+                        end
+                    end
+                end
+            end
+        end
+    end
+
+
+
+
+
+
+
+endmodule