fpga测试顶层 虚拟线模式

src/main/verilog/CDROne_fpga.v

@@ -0,0 +1,69 @@
+module CDROne_fpga(
+    input clock,
+    input resetn,
+    output [7:0] led
+
+//    output serDat_o_p,
+//    output serDat_o_n,
+
+//    input serDat_i_p,
+//    input serDat_i_n
+
+);
+
+wire serDat_o;
+wire serDat_i;
+wire clk100;
+wire clk400;
+
+
+//   IBUFDS #(
+//      .DIFF_TERM("FALSE"),       // Differential Termination
+//      .IBUF_LOW_PWR("TRUE"),     // Low power="TRUE", Highest performance="FALSE" 
+//      .IOSTANDARD("DEFAULT")     // Specify the input I/O standard
+//   ) IBUFDS_inst (
+//      .O(serDat_i),  // Buffer output
+//      .I(serDat_i_p),  // Diff_p buffer input (connect directly to top-level port)
+//      .IB(serDat_i_n) // Diff_n buffer input (connect directly to top-level port)
+//   );
+
+//   OBUFDS #(
+//      .IOSTANDARD("DEFAULT"), // Specify the output I/O standard
+//      .SLEW("SLOW")           // Specify the output slew rate
+//   ) OBUFDS_inst (
+//      .O(serDat_o_p),     // Diff_p output (connect directly to top-level port)
+//      .OB(serDat_o_n),   // Diff_n output (connect directly to top-level port)
+//      .I(serDat_o)      // Buffer input
+//   );
+
+clk_wiz_0 
+ (
+  // Clock out ports
+  .clk_out1(clk100),
+  .clk_out2(clk400),
+ // Clock in ports
+  .clk_in1(clock)
+ );
+
+
+
+
+CDROut_fpga(
+    .clock(clk100),
+    .reset(~resetn),
+    .serDat(serDat_o)
+);
+
+
+CDRIn_fpga(
+    .clock(clk100),
+    .reset(~resetn),
+    .overCLK(clk400),
+    .serDat(serDat_o),
+//    .serDat(serDat_i),
+    .led(led)
+
+);
+
+
+endmodule