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This commit is contained in:
Ruige Lee
2025-05-09 16:11:18 +08:00
parent 605f78c445
commit f05b61542c
2 changed files with 250 additions and 77 deletions
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132
src/main/scala/backBoard/shin/ShinTop.scala
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@@ -24,13 +24,6 @@ class ShinTopIO extends Bundle{
val timeStamp = Input(UInt(64.W))
val dSMdeq = Input( Vec(4, Bool()) )
val uSMenq = Input( Vec(4, Bool()) )
val sram_w = Vec( 4, new SRAM2kWRIO) //QSPI
val sram_r = Vec( 4, new SRAM2kRDIO) //QSPI
val modeSel = Input(Bool())
@@ -63,7 +56,7 @@ abstract class ShinTopBase extends Module{
val downCDROut = Module(new CDROut)
val upCDROut = Module(new CDROut)
val interface = Module(new Interface)
downCDRIn.io.serDat := io.dDatIn
downCDRIn.io.overCLK := io.clk8x
@@ -81,16 +74,7 @@ abstract class ShinTopBase extends Module{
}
val smUnit = Seq(
Module( new SMUnit(depth = 4) ),
Module( new SMUnit(depth = 4) ),
Module( new SMUnit(depth = 4) ),
Module( new SMUnit(depth = 4) ),
Module( new SMUnit(depth = 2) ),
Module( new SMUnit(depth = 2) ),
Module( new SMUnit(depth = 2) ),
Module( new SMUnit(depth = 2) ),
)
val sram = Seq(
for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
@@ -104,35 +88,38 @@ abstract class ShinTopBase extends Module{
)
val smUnit = Seq(
Module( new SMUnit(depth = 4) ),
Module( new SMUnit(depth = 4) ),
Module( new SMUnit(depth = 4) ),
Module( new SMUnit(depth = 4) ),
Module( new SMUnit(depth = 2) ),
Module( new SMUnit(depth = 2) ),
Module( new SMUnit(depth = 2) ),
Module( new SMUnit(depth = 2) ),
)
smUnit(0).io.sram_r <> io.sram_r(0)
smUnit(2).io.sram_r <> io.sram_r(1)
smUnit(4).io.sram_r <> io.sram_r(2)
smUnit(6).io.sram_r <> io.sram_r(3)
smUnit(1).io.sram_w := io.sram_w(0)
smUnit(3).io.sram_w := io.sram_w(1)
smUnit(5).io.sram_w := io.sram_w(2)
smUnit(7).io.sram_w := io.sram_w(3)
smUnit(0).io.deq := io.dSMdeq(0)
smUnit(2).io.deq := io.dSMdeq(1)
smUnit(4).io.deq := io.dSMdeq(2)
smUnit(6).io.deq := io.dSMdeq(3)
smUnit(1).io.enq := io.uSMenq(0)
smUnit(3).io.enq := io.uSMenq(1)
smUnit(5).io.enq := io.uSMenq(2)
smUnit(7).io.enq := io.uSMenq(3)
smUnit(0).io.sram_r <> interface.io.sram_r(0)
smUnit(2).io.sram_r <> interface.io.sram_r(1)
smUnit(4).io.sram_r <> interface.io.sram_r(2)
smUnit(6).io.sram_r <> interface.io.sram_r(3)
smUnit(1).io.sram_w := interface.io.sram_w(0)
smUnit(3).io.sram_w := interface.io.sram_w(1)
smUnit(5).io.sram_w := interface.io.sram_w(2)
smUnit(7).io.sram_w := interface.io.sram_w(3)
smUnit(0).io.deq := interface.io.dSMdeq(0)
smUnit(2).io.deq := interface.io.dSMdeq(1)
smUnit(4).io.deq := interface.io.dSMdeq(2)
smUnit(6).io.deq := interface.io.dSMdeq(3)
smUnit(1).io.enq := interface.io.uSMenq(0)
smUnit(3).io.enq := interface.io.uSMenq(1)
smUnit(5).io.enq := interface.io.uSMenq(2)
smUnit(7).io.enq := interface.io.uSMenq(3)
@@ -234,12 +221,45 @@ trait ShinTopMaster{ this: ShinTopBase =>
}
when( io.modeSel === true.B ){
smUnit(0).io.sram_w := masterParser.io.sram_w
smUnit(1).io.sram_r <> masterParser.io.sram_r
when( interface.io.txReq.bits.rxSM === 0.U ){
smUnit(0).io.sram_w := masterParser.io.sram_w
smUnit(0).io.enq := masterParser.io.rxEnq
} .elsewhen( interface.io.txReq.bits.rxSM === 1.U ){
smUnit(2).io.sram_w := masterParser.io.sram_w
smUnit(2).io.enq := masterParser.io.rxEnq
} .elsewhen( interface.io.txReq.bits.rxSM === 2.U ){
smUnit(4).io.sram_w := masterParser.io.sram_w
smUnit(4).io.enq := masterParser.io.rxEnq
} .elsewhen( interface.io.txReq.bits.rxSM === 3.U ){
smUnit(6).io.sram_w := masterParser.io.sram_w
smUnit(6).io.enq := masterParser.io.rxEnq
}
when( interface.io.txReq.bits.txSM === 0.U ){
smUnit(1).io.sram_r <> masterParser.io.sram_r
smUnit(1).io.deq := masterParser.io.txDeq
} .elsewhen( interface.io.txReq.bits.txSM === 1.U ){
smUnit(3).io.sram_r <> masterParser.io.sram_r
smUnit(3).io.deq := masterParser.io.txDeq
} .elsewhen( interface.io.txReq.bits.txSM === 2.U ){
smUnit(5).io.sram_r <> masterParser.io.sram_r
smUnit(5).io.deq := masterParser.io.txDeq
} .elsewhen( interface.io.txReq.bits.txSM === 3.U ){
smUnit(7).io.sram_r <> masterParser.io.sram_r
smUnit(7).io.deq := masterParser.io.txDeq
}
// _ := interface.io.smEnqAddr(0)
// _ := interface.io.smDeqAddr(1)
// _ := interface.io.smEnqAddr(2)
// _ := interface.io.smDeqAddr(3)
// _ := interface.io.smEnqAddr(4)
// _ := interface.io.smDeqAddr(5)
// _ := interface.io.smEnqAddr(6)
// _ := interface.io.smDeqAddr(7)
smUnit(0).io.enq := masterParser.io.rxEnq
smUnit(1).io.deq := masterParser.io.txDeq
}
@@ -264,15 +284,17 @@ trait ShinTopSlave{ this: ShinTopBase =>
slaveParser.io.timeStamp := io.timeStamp
val smEnqAddr = Vec(8, UInt(16.W)) //触发SM切换缓冲区的地址 （或读或写）
val smDeqAddr = Vec(8, UInt(16.W)) //触发SM切换缓冲区的地址 （或读或写）
slaveParser.io.trigAddr(0) := "hff".U
slaveParser.io.trigAddr(1) := "hff".U
slaveParser.io.trigAddr(2) := "hff".U
slaveParser.io.trigAddr(3) := "hff".U
slaveParser.io.trigAddr(4) := "hff".U
slaveParser.io.trigAddr(5) := "hff".U
slaveParser.io.trigAddr(6) := "hff".U
slaveParser.io.trigAddr(7) := "hff".U
slaveParser.io.trigAddr(0) := interface.io.smEnqAddr(0)
slaveParser.io.trigAddr(1) := interface.io.smDeqAddr(1)
slaveParser.io.trigAddr(2) := interface.io.smEnqAddr(2)
slaveParser.io.trigAddr(3) := interface.io.smDeqAddr(3)
slaveParser.io.trigAddr(4) := interface.io.smEnqAddr(4)
slaveParser.io.trigAddr(5) := interface.io.smDeqAddr(5)
slaveParser.io.trigAddr(6) := interface.io.smEnqAddr(6)
slaveParser.io.trigAddr(7) := interface.io.smDeqAddr(7)