From f05b61542c4fcd9c75cb7de0b294ca74b44f1c23 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Fri, 9 May 2025 16:11:18 +0800
Subject: [PATCH] =?UTF-8?q?SM=E4=B8=BB=E4=BB=8E=E7=BB=9F=E4=B8=80?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 src/main/scala/backBoard/shin/Interface.scala | 195 ++++++++++++++++--
 src/main/scala/backBoard/shin/ShinTop.scala   | 132 +++++++-----
 2 files changed, 250 insertions(+), 77 deletions(-)

diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index 1c85356..fc157dc 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -4,42 +4,48 @@ import chisel3._
 import chisel3.util._
 
 class CommonRegisterBundle extends Bundle{
-  val isMstNSlv = Bool()
+  val mstOrSlv  = UInt(2.W)
   val hwVersion = UInt(8.W)
   val hwSerial  = UInt(48.W)
   val busRate   = UInt(16.W)
 
-  val spiSel       = UInt(2.W)
+  // val spiSel       = UInt(2.W)
 
-  val isSoftReset  = Bool()
+  // val isSoftReset  = Bool()
   val encryptKey   = UInt(128.W)
   val isEncrypt    = Bool()
 
-  val upRecErrorCnt   = UInt(32.W)
-  val downRecErrorCnt = UInt(32.W)
-  val upForwardErrorCnt   = UInt(32.W)
-  val downForwardErrorCnt = UInt(32.W)
+  // val upRecErrorCnt   = UInt(32.W)
+  // val downRecErrorCnt = UInt(32.W)
+  // val upForwardErrorCnt   = UInt(32.W)
+  // val downForwardErrorCnt = UInt(32.W)
 
-  val qspiErrorCnt   = UInt(32.W)
-  val forwardCnt     = UInt(32.W)
-  val recByteCnt     = UInt(32.W)
-  val forwardByteCnt = UInt(32.W)
+  // val qspiErrorCnt   = UInt(32.W)
+  // val forwardCnt     = UInt(32.W)
+  // val recByteCnt     = UInt(32.W)
+  // val forwardByteCnt = UInt(32.W)
 
 
-  val wdtStatus   = UInt(16.W)
-  val wdtOverflow = UInt(8.W)
+  // val wdtStatus   = UInt(16.W)
+  // val wdtOverflow = UInt(8.W)
 
   val timeStamp = UInt(64.W)
   val deltaTime = UInt(32.W)
 
   val linkStatus = UInt(8.W)
 
+
+  val smEnqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
+  val smDeqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
+
+
+
 }
 
 class MasterRegisterBundle extends Bundle{
 
-  val isExInfoInit = Bool()
-  val isTxReq      = UInt(8.W)
+
+  val txSM         = UInt(2.W)
   val txStatus     = UInt(16.W)
 
 
@@ -96,6 +102,22 @@ class InterfaceIO extends Bundle{
   // val resp = Valid(new Bundle{
   //   datar = UInt(8.W)
   // })
+
+  val modeSel = Output(Bool())
+
+  val txReq = Valid(new Bundle{
+    val txSM = UInt(2.W)
+    val rxSM = UInt(2.W)
+  }) //发送请求和SM代号
+
+
+  val dSMdeq = Output( Vec(4, Bool()) )
+  val uSMenq = Output( Vec(4, Bool()) )
+
+  val sram_w = Flipped(Vec( 4, new SRAM2kWRIO)) //QSPI
+  val sram_r = Flipped(Vec( 4, new SRAM2kRDIO)) //QSPI
+
+
 }
 
 
@@ -105,20 +127,40 @@ abstract class InterfaceBase extends Module{
   val oSpi = Module(new SpiInterface)
   io.ospi <> oSpi.io.spi
 
-
   val cReg = Wire(new CommonRegisterBundle)
   val mReg = Wire(new MasterRegisterBundle)
   val sReg = Wire(new SlaveRegisterBundle)
 
+  val isSysInit = cReg.mstOrSlv =/= 0.U
+
   def AcquireReg(addr: UInt): UInt = {
-    Mux1H(Seq(
+    Mux1H(
+      Seq(
+      (addr === "h0".U) -> cReg.mstOrSlv,
+      (addr === "h1".U) -> cReg.hwVersion,
+      ) ++
 
-    ))
+      ((0 until 6).map{ i =>
+        (addr === ("h2".U + i.U) ) -> cReg.hwSerial( 8*i+7,8*i+0),
+      }) ++
+      
+      Seq(
+        (addr === "h8".U) -> cReg.busRate( 7,0),
+        (addr === "h9".U) -> cReg.busRate(15,8),        
+      ) ++
+
+      ((0 until 16).map{ i =>
+        (addr === ("h80".U + i.U) ) -> cReg.encryptKey( 8*i+7,8*i+0),
+      }) ++
+
+      Seq()
+
+    )
   }
 
-  def UpdateReg( addr: UInt ) = {
+
     
-  }
+
 
 
 }
@@ -129,15 +171,118 @@ trait InterfaceMCUop{ this: InterfaceBase =>
 
   oSpi.io.addrSel = Output(UInt(16.W))
   oSpi.io.dataw   = Output( UInt(8.W) )
-  oSpi.io.datar   := RegEnable( AcquireReg(addr = oSpi.io.addrSel), 0.U, oSpi.io.isEnR )
+  oSpi.io.datar   :=
+    MuxCase( 0.U, Array(
+      ((oSpi.io.addrSel & "hFF00".U) === "h0000".U) -> RegEnable( AcquireReg(addr = oSpi.io.addrSel), 0.U, oSpi.io.isEnR ),
+      ((oSpi.io.addrSel & "hFF00".U) === "h0800".U) -> smUnit(0).io.sram_r.datar,
+      ((oSpi.io.addrSel & "hFF00".U) === "h1000".U) -> 0.U,
+      ((oSpi.io.addrSel & "hFF00".U) === "h1800".U) -> smUnit(2).io.sram_r.datar,
+      ((oSpi.io.addrSel & "hFF00".U) === "h2000".U) -> 0.U,
+      ((oSpi.io.addrSel & "hFF00".U) === "h2800".U) -> smUnit(4).io.sram_r.datar,
+      ((oSpi.io.addrSel & "hFF00".U) === "h3000".U) -> 0.U,
+      ((oSpi.io.addrSel & "hFF00".U) === "h3800".U) -> smUnit(6).io.sram_r.datar,
+      ((oSpi.io.addrSel & "hFF00".U) === "h4000".U) -> 0.U,
+    ))
+
   oSpi.io.isEnW   = Output(Bool())
+
+  val isEnW = oSpi.io.isEnW
+  val addrSel = oSpi.io.addrSel
+  val dataw = oSpi.io.dataw
+  val isEnR = oSpi.io.isEnR
+
+  cReg.mstOrSlv  := RegEnable( dataw(1,0), 0.U, isEnW & addrSel === "h0".U & cReg.mstOrSlv === 0.U )
+  cReg.hwVersion := RegEnable( dataw     , 0.U, isEnW & addrSel === "h1".U & cReg.mstOrSlv === 0.U )
+
+  cReg.hwSerial := 
+    Cat(
+      (0 until 6).map{ i =>
+      RegEnable( dataw, 0.U, isEnW & addrSel === ("h2".U + i.U) & cReg.mstOrSlv === 0.U )
+      }.reverse
+    )
   
+  cReg.busRate :=
+    Cat(
+      RegEnable( dataw, 0.U, isEnW & addrSel === "h9".U & cReg.mstOrSlv === 0.U ),
+      RegEnable( dataw, 0.U, isEnW & addrSel === "h8".U & cReg.mstOrSlv === 0.U )
+    )
+
+  cReg.encryptKey :=
+    Cat(
+      (0 until 16).map{ i =>
+        RegEnable( dataw, 0.U, isEnW & addrSel === ("h80".U + i.U) & cReg.mstOrSlv === 0.U )
+      }.reserve
+    )
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
 }
 
 trait InterfaceCheckSM{ this: InterfaceBase =>
-  when( oSpi.io.isEnR & oSpi.io.addrSel ===  ){
+  mReg.txSM := RegEnable( dataw(2,1), 0.U, isEnW & addrSel === "h20".U )
+  mReg.rxSM := RegEnable( dataw(4,3), 0.U, isEnW & addrSel === "h20".U )
 
+  for( i <- 0 until 8 ){
+    cReg.smEnqAddr(i) := 
+      Cat(
+        RegEnable( dataw, 0.U, isEnW & addrSel === "h20".U ),
+        RegEnable( dataw, 0.U, isEnW & addrSel === "h20".U )
+      )
+    cReg.smDeqAddr(i) := 
+      Cat(
+        RegEnable( dataw, 0.U, isEnW & addrSel === "h20".U ),
+        RegEnable( dataw, 0.U, isEnW & addrSel === "h20".U )
+      )
   }
+
+
+  io.sram_r(0).addrr := addrSel
+  io.sram_r(1).addrr := addrSel
+  io.sram_r(2).addrr := addrSel
+  io.sram_r(3).addrr := addrSel
+
+  io.sram_r(0).enr   := isEnR & (( addrSel & "hF800".U ) === "h0800".U)
+  io.sram_r(1).enr   := isEnR & (( addrSel & "hF800".U ) === "h1800".U)
+  io.sram_r(2).enr   := isEnR & (( addrSel & "hF800".U ) === "h2800".U)
+  io.sram_r(3).enr   := isEnR & (( addrSel & "hF800".U ) === "h3800".U)
+
+  io.sram_w(0).addrw := addrSel
+  io.sram_w(1).addrw := addrSel
+  io.sram_w(2).addrw := addrSel
+  io.sram_w(3).addrw := addrSel
+
+  io.sram_w(0).dataw := dataw
+  io.sram_w(1).dataw := dataw
+  io.sram_w(2).dataw := dataw
+  io.sram_w(3).dataw := dataw
+
+  io.sram_w(0).enw   := isEnW & (( addrSel & "hF800".U ) === "h1000".U)
+  io.sram_w(1).enw   := isEnW & (( addrSel & "hF800".U ) === "h2000".U)
+  io.sram_w(2).enw   := isEnW & (( addrSel & "hF800".U ) === "h3000".U)
+  io.sram_w(3).enw   := isEnW & (( addrSel & "hF800".U ) === "h4000".U)
+
+  io.dSMdeq(0) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === smDeqAddr(0))
+  io.dSMdeq(1) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === smDeqAddr(2))
+  io.dSMdeq(2) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === smDeqAddr(4))
+  io.dSMdeq(3) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === smDeqAddr(6))
+
+  io.uSMenq(0) := isEnW & (( addrSel & "hF800".U ) === "h1000".U) & (addrSel(10,0) === smEnqAddr(1))
+  io.uSMenq(1) := isEnW & (( addrSel & "hF800".U ) === "h2000".U) & (addrSel(10,0) === smEnqAddr(3))
+  io.uSMenq(2) := isEnW & (( addrSel & "hF800".U ) === "h3000".U) & (addrSel(10,0) === smEnqAddr(5))
+  io.uSMenq(3) := isEnW & (( addrSel & "hF800".U ) === "h4000".U) & (addrSel(10,0) === smEnqAddr(7))
 }
 
 trait InterfaceLVDSop{ this: InterfaceBase =>
@@ -150,4 +295,10 @@ class Interface extends InterfaceBase
 with InterfaceMCUop
 {
 
+  io.modeSel := cReg.mstOrSlv === "h1".U
+
+  io.txReq.bits.txSM  := mReg.txSM
+  io.txReq.bits.rxSM  := mReg.rxSM
+  io.txReq.valid := isEnW & addrSel === "h20".U & dataw.extract(0) === "b1".U
+
 }
\ No newline at end of file
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index d5c44d1..4c266e6 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -24,13 +24,6 @@ class ShinTopIO extends Bundle{
 
   val timeStamp = Input(UInt(64.W))
 
-  val dSMdeq = Input( Vec(4, Bool()) )
-  val uSMenq = Input( Vec(4, Bool()) )
-
-  val sram_w = Vec( 4, new SRAM2kWRIO) //QSPI
-  val sram_r = Vec( 4, new SRAM2kRDIO) //QSPI
-
-
   val modeSel = Input(Bool())
 
 
@@ -63,7 +56,7 @@ abstract class ShinTopBase extends Module{
   val downCDROut = Module(new CDROut)
   val upCDROut   = Module(new CDROut)
 
-
+  val interface = Module(new Interface)
 
   downCDRIn.io.serDat  := io.dDatIn
   downCDRIn.io.overCLK := io.clk8x
@@ -81,16 +74,7 @@ abstract class ShinTopBase extends Module{
   }
 
 
-  val smUnit = Seq(
-    Module( new SMUnit(depth = 4) ),
-    Module( new SMUnit(depth = 4) ),
-    Module( new SMUnit(depth = 4) ),
-    Module( new SMUnit(depth = 4) ),
-    Module( new SMUnit(depth = 2) ),
-    Module( new SMUnit(depth = 2) ),
-    Module( new SMUnit(depth = 2) ),
-    Module( new SMUnit(depth = 2) ),
-  )
+
 
   val sram = Seq(
     for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
@@ -104,35 +88,38 @@ abstract class ShinTopBase extends Module{
   )
 
 
+  val smUnit = Seq(
+    Module( new SMUnit(depth = 4) ),
+    Module( new SMUnit(depth = 4) ),
+    Module( new SMUnit(depth = 4) ),
+    Module( new SMUnit(depth = 4) ),
+    Module( new SMUnit(depth = 2) ),
+    Module( new SMUnit(depth = 2) ),
+    Module( new SMUnit(depth = 2) ),
+    Module( new SMUnit(depth = 2) ),
+  )
 
 
-  smUnit(0).io.sram_r <> io.sram_r(0)
-  smUnit(2).io.sram_r <> io.sram_r(1)
-  smUnit(4).io.sram_r <> io.sram_r(2)
-  smUnit(6).io.sram_r <> io.sram_r(3)
-
-
-
-  smUnit(1).io.sram_w := io.sram_w(0)
-  smUnit(3).io.sram_w := io.sram_w(1)
-  smUnit(5).io.sram_w := io.sram_w(2)
-  smUnit(7).io.sram_w := io.sram_w(3)
-
-
-  smUnit(0).io.deq := io.dSMdeq(0)
-  smUnit(2).io.deq := io.dSMdeq(1)
-  smUnit(4).io.deq := io.dSMdeq(2)
-  smUnit(6).io.deq := io.dSMdeq(3)
-
-
-  smUnit(1).io.enq := io.uSMenq(0)
-  smUnit(3).io.enq := io.uSMenq(1)
-  smUnit(5).io.enq := io.uSMenq(2)
-  smUnit(7).io.enq := io.uSMenq(3)
-
-
+  smUnit(0).io.sram_r <> interface.io.sram_r(0)
+  smUnit(2).io.sram_r <> interface.io.sram_r(1)
+  smUnit(4).io.sram_r <> interface.io.sram_r(2)
+  smUnit(6).io.sram_r <> interface.io.sram_r(3)
+
+  smUnit(1).io.sram_w := interface.io.sram_w(0)
+  smUnit(3).io.sram_w := interface.io.sram_w(1)
+  smUnit(5).io.sram_w := interface.io.sram_w(2)
+  smUnit(7).io.sram_w := interface.io.sram_w(3)
+
+  smUnit(0).io.deq := interface.io.dSMdeq(0)
+  smUnit(2).io.deq := interface.io.dSMdeq(1)
+  smUnit(4).io.deq := interface.io.dSMdeq(2)
+  smUnit(6).io.deq := interface.io.dSMdeq(3)
 
 
+  smUnit(1).io.enq := interface.io.uSMenq(0)
+  smUnit(3).io.enq := interface.io.uSMenq(1)
+  smUnit(5).io.enq := interface.io.uSMenq(2)
+  smUnit(7).io.enq := interface.io.uSMenq(3)
 
 
 
@@ -234,12 +221,45 @@ trait ShinTopMaster{ this: ShinTopBase =>
   }
 
   when( io.modeSel === true.B ){
-    smUnit(0).io.sram_w := masterParser.io.sram_w
-    smUnit(1).io.sram_r <> masterParser.io.sram_r
+
+    when( interface.io.txReq.bits.rxSM === 0.U ){
+      smUnit(0).io.sram_w := masterParser.io.sram_w
+      smUnit(0).io.enq    := masterParser.io.rxEnq
+    } .elsewhen( interface.io.txReq.bits.rxSM === 1.U ){
+      smUnit(2).io.sram_w := masterParser.io.sram_w
+      smUnit(2).io.enq    := masterParser.io.rxEnq
+    } .elsewhen( interface.io.txReq.bits.rxSM === 2.U ){
+      smUnit(4).io.sram_w := masterParser.io.sram_w
+      smUnit(4).io.enq    := masterParser.io.rxEnq
+    } .elsewhen( interface.io.txReq.bits.rxSM === 3.U ){
+      smUnit(6).io.sram_w := masterParser.io.sram_w
+      smUnit(6).io.enq    := masterParser.io.rxEnq
+    }
+
+    when( interface.io.txReq.bits.txSM === 0.U ){
+      smUnit(1).io.sram_r <> masterParser.io.sram_r
+      smUnit(1).io.deq    := masterParser.io.txDeq
+    } .elsewhen( interface.io.txReq.bits.txSM === 1.U ){
+      smUnit(3).io.sram_r <> masterParser.io.sram_r
+      smUnit(3).io.deq    := masterParser.io.txDeq
+    } .elsewhen( interface.io.txReq.bits.txSM === 2.U ){
+      smUnit(5).io.sram_r <> masterParser.io.sram_r
+      smUnit(5).io.deq    := masterParser.io.txDeq
+    } .elsewhen( interface.io.txReq.bits.txSM === 3.U ){
+      smUnit(7).io.sram_r <> masterParser.io.sram_r
+      smUnit(7).io.deq    := masterParser.io.txDeq
+    }
+
+    // _ := interface.io.smEnqAddr(0)
+    // _ := interface.io.smDeqAddr(1)
+    // _ := interface.io.smEnqAddr(2)
+    // _ := interface.io.smDeqAddr(3)
+    // _ := interface.io.smEnqAddr(4)
+    // _ := interface.io.smDeqAddr(5)
+    // _ := interface.io.smEnqAddr(6)
+    // _ := interface.io.smDeqAddr(7)
 
 
-    smUnit(0).io.enq := masterParser.io.rxEnq
-    smUnit(1).io.deq := masterParser.io.txDeq
 
   }
 
@@ -264,15 +284,17 @@ trait ShinTopSlave{ this: ShinTopBase =>
 
   slaveParser.io.timeStamp := io.timeStamp
 
+  val smEnqAddr = Vec(8, UInt(16.W)) //触发SM切换缓冲区的地址 （或读或写）
+  val smDeqAddr = Vec(8, UInt(16.W)) //触发SM切换缓冲区的地址 （或读或写）
 
-  slaveParser.io.trigAddr(0) := "hff".U
-  slaveParser.io.trigAddr(1) := "hff".U
-  slaveParser.io.trigAddr(2) := "hff".U
-  slaveParser.io.trigAddr(3) := "hff".U
-  slaveParser.io.trigAddr(4) := "hff".U
-  slaveParser.io.trigAddr(5) := "hff".U
-  slaveParser.io.trigAddr(6) := "hff".U
-  slaveParser.io.trigAddr(7) := "hff".U
+  slaveParser.io.trigAddr(0) := interface.io.smEnqAddr(0)
+  slaveParser.io.trigAddr(1) := interface.io.smDeqAddr(1)
+  slaveParser.io.trigAddr(2) := interface.io.smEnqAddr(2)
+  slaveParser.io.trigAddr(3) := interface.io.smDeqAddr(3)
+  slaveParser.io.trigAddr(4) := interface.io.smEnqAddr(4)
+  slaveParser.io.trigAddr(5) := interface.io.smDeqAddr(5)
+  slaveParser.io.trigAddr(6) := interface.io.smEnqAddr(6)
+  slaveParser.io.trigAddr(7) := interface.io.smDeqAddr(7)