SM主从统一
This commit is contained in:
Ruige Lee
@@ -4,42 +4,48 @@ import chisel3._
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import chisel3.util._
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class CommonRegisterBundle extends Bundle{
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val isMstNSlv = Bool()
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val mstOrSlv = UInt(2.W)
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val hwVersion = UInt(8.W)
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val hwSerial = UInt(48.W)
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val busRate = UInt(16.W)
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val spiSel = UInt(2.W)
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// val spiSel = UInt(2.W)
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val isSoftReset = Bool()
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// val isSoftReset = Bool()
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val encryptKey = UInt(128.W)
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val isEncrypt = Bool()
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val upRecErrorCnt = UInt(32.W)
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val downRecErrorCnt = UInt(32.W)
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val upForwardErrorCnt = UInt(32.W)
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val downForwardErrorCnt = UInt(32.W)
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// val upRecErrorCnt = UInt(32.W)
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// val downRecErrorCnt = UInt(32.W)
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// val upForwardErrorCnt = UInt(32.W)
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// val downForwardErrorCnt = UInt(32.W)
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val qspiErrorCnt = UInt(32.W)
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val forwardCnt = UInt(32.W)
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val recByteCnt = UInt(32.W)
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val forwardByteCnt = UInt(32.W)
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// val qspiErrorCnt = UInt(32.W)
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// val forwardCnt = UInt(32.W)
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// val recByteCnt = UInt(32.W)
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// val forwardByteCnt = UInt(32.W)
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val wdtStatus = UInt(16.W)
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val wdtOverflow = UInt(8.W)
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// val wdtStatus = UInt(16.W)
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// val wdtOverflow = UInt(8.W)
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val timeStamp = UInt(64.W)
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val deltaTime = UInt(32.W)
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val linkStatus = UInt(8.W)
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val smEnqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
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val smDeqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
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}
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class MasterRegisterBundle extends Bundle{
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val isExInfoInit = Bool()
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val isTxReq = UInt(8.W)
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val txSM = UInt(2.W)
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val txStatus = UInt(16.W)
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@@ -96,6 +102,22 @@ class InterfaceIO extends Bundle{
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// val resp = Valid(new Bundle{
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// datar = UInt(8.W)
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// })
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val modeSel = Output(Bool())
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val txReq = Valid(new Bundle{
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val txSM = UInt(2.W)
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val rxSM = UInt(2.W)
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}) //发送请求和SM代号
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val dSMdeq = Output( Vec(4, Bool()) )
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val uSMenq = Output( Vec(4, Bool()) )
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val sram_w = Flipped(Vec( 4, new SRAM2kWRIO)) //QSPI
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val sram_r = Flipped(Vec( 4, new SRAM2kRDIO)) //QSPI
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}
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@@ -105,20 +127,40 @@ abstract class InterfaceBase extends Module{
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val oSpi = Module(new SpiInterface)
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io.ospi <> oSpi.io.spi
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val cReg = Wire(new CommonRegisterBundle)
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val mReg = Wire(new MasterRegisterBundle)
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val sReg = Wire(new SlaveRegisterBundle)
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val isSysInit = cReg.mstOrSlv =/= 0.U
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def AcquireReg(addr: UInt): UInt = {
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Mux1H(Seq(
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Mux1H(
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Seq(
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(addr === "h0".U) -> cReg.mstOrSlv,
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(addr === "h1".U) -> cReg.hwVersion,
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) ++
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))
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((0 until 6).map{ i =>
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(addr === ("h2".U + i.U) ) -> cReg.hwSerial( 8*i+7,8*i+0),
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}) ++
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Seq(
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(addr === "h8".U) -> cReg.busRate( 7,0),
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(addr === "h9".U) -> cReg.busRate(15,8),
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) ++
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((0 until 16).map{ i =>
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(addr === ("h80".U + i.U) ) -> cReg.encryptKey( 8*i+7,8*i+0),
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}) ++
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Seq()
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)
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}
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def UpdateReg( addr: UInt ) = {
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}
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}
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@@ -129,15 +171,118 @@ trait InterfaceMCUop{ this: InterfaceBase =>
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oSpi.io.addrSel = Output(UInt(16.W))
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oSpi.io.dataw = Output( UInt(8.W) )
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oSpi.io.datar := RegEnable( AcquireReg(addr = oSpi.io.addrSel), 0.U, oSpi.io.isEnR )
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oSpi.io.datar :=
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MuxCase( 0.U, Array(
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((oSpi.io.addrSel & "hFF00".U) === "h0000".U) -> RegEnable( AcquireReg(addr = oSpi.io.addrSel), 0.U, oSpi.io.isEnR ),
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((oSpi.io.addrSel & "hFF00".U) === "h0800".U) -> smUnit(0).io.sram_r.datar,
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((oSpi.io.addrSel & "hFF00".U) === "h1000".U) -> 0.U,
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((oSpi.io.addrSel & "hFF00".U) === "h1800".U) -> smUnit(2).io.sram_r.datar,
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((oSpi.io.addrSel & "hFF00".U) === "h2000".U) -> 0.U,
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((oSpi.io.addrSel & "hFF00".U) === "h2800".U) -> smUnit(4).io.sram_r.datar,
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((oSpi.io.addrSel & "hFF00".U) === "h3000".U) -> 0.U,
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((oSpi.io.addrSel & "hFF00".U) === "h3800".U) -> smUnit(6).io.sram_r.datar,
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((oSpi.io.addrSel & "hFF00".U) === "h4000".U) -> 0.U,
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))
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oSpi.io.isEnW = Output(Bool())
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val isEnW = oSpi.io.isEnW
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val addrSel = oSpi.io.addrSel
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val dataw = oSpi.io.dataw
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val isEnR = oSpi.io.isEnR
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cReg.mstOrSlv := RegEnable( dataw(1,0), 0.U, isEnW & addrSel === "h0".U & cReg.mstOrSlv === 0.U )
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cReg.hwVersion := RegEnable( dataw , 0.U, isEnW & addrSel === "h1".U & cReg.mstOrSlv === 0.U )
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cReg.hwSerial :=
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Cat(
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(0 until 6).map{ i =>
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RegEnable( dataw, 0.U, isEnW & addrSel === ("h2".U + i.U) & cReg.mstOrSlv === 0.U )
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}.reverse
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)
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cReg.busRate :=
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Cat(
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RegEnable( dataw, 0.U, isEnW & addrSel === "h9".U & cReg.mstOrSlv === 0.U ),
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RegEnable( dataw, 0.U, isEnW & addrSel === "h8".U & cReg.mstOrSlv === 0.U )
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)
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cReg.encryptKey :=
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Cat(
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(0 until 16).map{ i =>
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RegEnable( dataw, 0.U, isEnW & addrSel === ("h80".U + i.U) & cReg.mstOrSlv === 0.U )
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}.reserve
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)
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}
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trait InterfaceCheckSM{ this: InterfaceBase =>
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when( oSpi.io.isEnR & oSpi.io.addrSel === ){
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mReg.txSM := RegEnable( dataw(2,1), 0.U, isEnW & addrSel === "h20".U )
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mReg.rxSM := RegEnable( dataw(4,3), 0.U, isEnW & addrSel === "h20".U )
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for( i <- 0 until 8 ){
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cReg.smEnqAddr(i) :=
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Cat(
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RegEnable( dataw, 0.U, isEnW & addrSel === "h20".U ),
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RegEnable( dataw, 0.U, isEnW & addrSel === "h20".U )
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)
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cReg.smDeqAddr(i) :=
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Cat(
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RegEnable( dataw, 0.U, isEnW & addrSel === "h20".U ),
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RegEnable( dataw, 0.U, isEnW & addrSel === "h20".U )
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)
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}
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io.sram_r(0).addrr := addrSel
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io.sram_r(1).addrr := addrSel
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io.sram_r(2).addrr := addrSel
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io.sram_r(3).addrr := addrSel
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io.sram_r(0).enr := isEnR & (( addrSel & "hF800".U ) === "h0800".U)
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io.sram_r(1).enr := isEnR & (( addrSel & "hF800".U ) === "h1800".U)
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io.sram_r(2).enr := isEnR & (( addrSel & "hF800".U ) === "h2800".U)
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io.sram_r(3).enr := isEnR & (( addrSel & "hF800".U ) === "h3800".U)
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io.sram_w(0).addrw := addrSel
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io.sram_w(1).addrw := addrSel
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io.sram_w(2).addrw := addrSel
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io.sram_w(3).addrw := addrSel
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io.sram_w(0).dataw := dataw
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io.sram_w(1).dataw := dataw
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io.sram_w(2).dataw := dataw
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io.sram_w(3).dataw := dataw
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io.sram_w(0).enw := isEnW & (( addrSel & "hF800".U ) === "h1000".U)
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io.sram_w(1).enw := isEnW & (( addrSel & "hF800".U ) === "h2000".U)
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io.sram_w(2).enw := isEnW & (( addrSel & "hF800".U ) === "h3000".U)
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io.sram_w(3).enw := isEnW & (( addrSel & "hF800".U ) === "h4000".U)
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io.dSMdeq(0) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === smDeqAddr(0))
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io.dSMdeq(1) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === smDeqAddr(2))
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io.dSMdeq(2) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === smDeqAddr(4))
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io.dSMdeq(3) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === smDeqAddr(6))
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io.uSMenq(0) := isEnW & (( addrSel & "hF800".U ) === "h1000".U) & (addrSel(10,0) === smEnqAddr(1))
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io.uSMenq(1) := isEnW & (( addrSel & "hF800".U ) === "h2000".U) & (addrSel(10,0) === smEnqAddr(3))
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io.uSMenq(2) := isEnW & (( addrSel & "hF800".U ) === "h3000".U) & (addrSel(10,0) === smEnqAddr(5))
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io.uSMenq(3) := isEnW & (( addrSel & "hF800".U ) === "h4000".U) & (addrSel(10,0) === smEnqAddr(7))
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}
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trait InterfaceLVDSop{ this: InterfaceBase =>
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@@ -150,4 +295,10 @@ class Interface extends InterfaceBase
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with InterfaceMCUop
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{
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io.modeSel := cReg.mstOrSlv === "h1".U
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io.txReq.bits.txSM := mReg.txSM
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io.txReq.bits.rxSM := mReg.rxSM
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io.txReq.valid := isEnW & addrSel === "h20".U & dataw.extract(0) === "b1".U
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}
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