SRAM规格不够大

src/main/scala/backBoard/MirrorSRAM.scala

@@ -335,3 +335,59 @@ class MirrorSRAMDP extends BlackBox with HasBlackBoxInline {
 }
 
 
+
+
+class MirrorSRAMSpi() extends BlackBox with HasBlackBoxInline {
+  class MirrorSRAMSpiIO extends Bundle{
+      val addrr  = Input(UInt(4.W))
+      val addrw  = Input(UInt(4.W))
+
+      val dataw = Input( UInt(248.W) )
+      val datar = Output( UInt(248.W) )
+      val enw   = Input(Bool())
+      val enr   = Input(Bool())
+
+      val clockr = Input(Bool())
+      val clockw = Input(Bool())
+
+  }
+  val io: MirrorSRAMSpiIO = IO(new MirrorSRAMSpiIO)
+
+ setInline("MirrorSRAMSpi.v",
+              """
+      | module MirrorSRAMSpi(
+      |  	input [3:0] addrr,
+      |  	input [3:0] addrw,
+      |
+      |  	input [247:0] dataw,
+      |  	output [247:0] datar,
+      |  	input enw,
+      |  	input enr,
+      |  
+      |  	input clockr,
+      |  	input clockw
+      |  );
+      |  
+      |  	reg [247:0] ram[0:15];
+      |  	reg [247:0] data_r_reg;
+      |  
+      |  	always @(posedge clockw) begin
+      |  		if(enw) begin
+      |  			ram[addrw] <= #1 dataw;					
+      |  		end
+      |   end
+      | 
+      |
+      |   always @(posedge clockr) begin
+      |     if(enr) begin
+      |  		  data_r_reg <= #1 ram[addrr];
+      |     end
+      |   end
+      |  
+      |  
+      |  	assign datar = data_r_reg;
+      |  
+      |   
+      |endmodule
+    """.stripMargin)
+}