diff --git a/src/main/scala/backBoard/MirrorSRAM.scala b/src/main/scala/backBoard/MirrorSRAM.scala
index 822604e..fdc7c96 100644
--- a/src/main/scala/backBoard/MirrorSRAM.scala
+++ b/src/main/scala/backBoard/MirrorSRAM.scala
@@ -335,3 +335,59 @@ class MirrorSRAMDP extends BlackBox with HasBlackBoxInline {
 }
 
 
+
+
+class MirrorSRAMSpi() extends BlackBox with HasBlackBoxInline {
+  class MirrorSRAMSpiIO extends Bundle{
+      val addrr  = Input(UInt(4.W))
+      val addrw  = Input(UInt(4.W))
+
+      val dataw = Input( UInt(248.W) )
+      val datar = Output( UInt(248.W) )
+      val enw   = Input(Bool())
+      val enr   = Input(Bool())
+
+      val clockr = Input(Bool())
+      val clockw = Input(Bool())
+
+  }
+  val io: MirrorSRAMSpiIO = IO(new MirrorSRAMSpiIO)
+
+ setInline("MirrorSRAMSpi.v",
+              """
+      | module MirrorSRAMSpi(
+      |  	input [3:0] addrr,
+      |  	input [3:0] addrw,
+      |
+      |  	input [247:0] dataw,
+      |  	output [247:0] datar,
+      |  	input enw,
+      |  	input enr,
+      |  
+      |  	input clockr,
+      |  	input clockw
+      |  );
+      |  
+      |  	reg [247:0] ram[0:15];
+      |  	reg [247:0] data_r_reg;
+      |  
+      |  	always @(posedge clockw) begin
+      |  		if(enw) begin
+      |  			ram[addrw] <= #1 dataw;					
+      |  		end
+      |   end
+      | 
+      |
+      |   always @(posedge clockr) begin
+      |     if(enr) begin
+      |  		  data_r_reg <= #1 ram[addrr];
+      |     end
+      |   end
+      |  
+      |  
+      |  	assign datar = data_r_reg;
+      |  
+      |   
+      |endmodule
+    """.stripMargin)
+}
\ No newline at end of file
diff --git a/src/main/scala/backBoard/SpiSlv.scala b/src/main/scala/backBoard/SpiSlv.scala
index 217ad51..7d1c6ef 100644
--- a/src/main/scala/backBoard/SpiSlv.scala
+++ b/src/main/scala/backBoard/SpiSlv.scala
@@ -13,7 +13,12 @@ trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
   val csn   = Wire(Bool())
   val clk100M = Wire(Bool())
 
-  val localReg = for( i <- 0 until page ) yield {Reg(Vec(31, UInt(8.W)))}
+  val localReg = Module(new MirrorSRAMSpi)
+  localReg.io.clockw := clock.asBool
+  localReg.io.clockr := clock.asBool
+  localReg.io.addrr := statusPage
+  localReg.io.enr   := true.B
+
   val localUpdate = RegInit(0.U(16.W))
 
 
@@ -31,12 +36,10 @@ trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
   val cmd_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(8.W)) }
   val pageSel = cmd_100M(7,4)
   val spiCmd  = cmd_100M(3,0)
-  val localPage = PriorityMux( ( 0 until page ).map{ i => ( i.U === pageSel ) -> localReg(i) } )
+
 
   val cnt_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(4.W)) }
 
-  // val misoReg      = withClockAndReset( clk100M.asClock, reset ){ Reg(Bool()) }
-
 
   withClockAndReset( clk100M.asClock, reset ){//100M
 
@@ -47,7 +50,7 @@ trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
       cmd_100M := Cat( cmd_100M(6,0), shiftMOSI(1) )
       cnt_100M := cnt_100M + 1.U
     } .elsewhen( isSckNegedge & ~shiftCSn(1) & cnt_100M === 8.U ){
-      exReg_100M := Mux( spiCmd.extract(1), Cat( localUpdate, 0.U((8*29).W) ), Cat( localPage.reverse) )
+      exReg_100M := Mux( spiCmd.extract(1), Cat( localUpdate, 0.U((8*29).W) ), localReg.io.datar )
       cnt_100M := cnt_100M + 1.U
     } .elsewhen( isSckPosedge & ~shiftCSn(1) & cnt_100M === 9.U ){
       // misoReg := exReg_100M.extract(exReg_100M.getWidth-1)
@@ -79,33 +82,42 @@ with BackBoardSpiSlv{
 
   val shiftCSn_10M = ShiftRegisters(csn, 3, true.B, true.B)
 
-  for( i <- 0 until page ){
+
+
+  when( isCrcPass ){
+    localUpdate := localUpdate & ~( 1.U << downRegTemp(0)(3,0) )
+  } .elsewhen( ~shiftCSn_10M(2) & shiftCSn_10M(1) & spiCmd === 3.U ){
+    localUpdate := localUpdate & (~exReg_100M(15,0))
+  }
+  
+
+
+
+
+
+
+  // for( i <- 0 until page ){
 
     when( isCrcPass ){
-      when( downRegTemp(0)(3,0) === i.U ){
-        localUpdate := localUpdate & ~( 1.U << i )
-        for( j <- 1 until 32 ) {
-          localReg(i)(j-1) := downRegTemp(j)
-        }
-      }
+      localReg.io.addrw := downRegTemp(0)(3,0)
+      localReg.io.enw   := true.B
+      localReg.io.dataw := Cat( (1 until 32).map{ i => downRegTemp(i) }.reverse )
     } .elsewhen( ~shiftCSn_10M(2) & shiftCSn_10M(1) & spiCmd === 1.U ){
-      when( i.U === pageSel ){
-        for( j <- 0 until 31 ) {
-          localReg(i)(30-j) := exReg_100M(8*j+7,8*j)
-        }        
-      }
-    } .elsewhen( ~shiftCSn_10M(2) & shiftCSn_10M(1) & spiCmd === 3.U ){
-      localUpdate := localUpdate & (~exReg_100M(15,0))
+      localReg.io.addrw := pageSel
+      localReg.io.enw   := true.B
+      localReg.io.dataw := exReg_100M
+    } .otherwise{
+      localReg.io.addrw := DontCare
+      localReg.io.enw   := false.B
+      localReg.io.dataw := DontCare
     }
 
-    when( statusPage === i.U ){
-      for( j <- 1 until 32 ) {
-        upReg(j) := localReg(i)(j-1)
-      }
-    }
-  }
 
 
+    for( i <- 0 until 31 ) {
+      upReg(i+1) := localReg.io.datar((30-i)*8+7, (30-i)*8)
+    }
+
 
 }