增加vcs下仿真文件，尚未调试通过，仅备份

tb/shinTest/Makefile_vcs

@@ -0,0 +1,53 @@
+.PHONY:com sim clean
+
+OUTPUT = shin_test
+
+VCS = vcs -sverilog +v2k -timescale=1ns/1ps                             \
+	-debug_all                                                    \
+	-full64                                                       \
+	-o ${OUTPUT}                                                  \
+	-l compile.log                                                \
+
+SIM = ./${OUTPUT} -l run.log
+
+testShin_vcs:
+	python3 ./shinTest/gen_pkt.py
+	${VCS} -f ./shinTest_vcs.f
+	${SIM}
+sim:
+	${SIM}
+
+testShin:
+	./shinTest/gen_pkt.py
+	mkdir -p generated/log
+	rm -rf generated/log/*
+	iverilog -Wall  \
+	-o ./generated/shinTest.iverilog  \
+	-y ./generated/shin \
+	-I ./generated/shin \
+	-D RANDOMIZE_REG_INIT \
+	./shinTest/ShinTopSpiTb.v
+	vvp  -N ./generated/shinTest.iverilog -lxt2  -fst || true
+	./shinTest/check_testcase.py
+
+testShinClk:
+	./shinTest/gen_pkt_clk.py
+	mkdir -p generated/log
+	rm -rf generated/log/*
+	iverilog -Wall  \
+	-o ./generated/shinTest_clk.iverilog  \
+	-y ./generated/shin \
+	-I ./generated/shin \
+	-D RANDOMIZE_REG_INIT \
+	./shinTest/ShinTopSpiTb_clk.v
+	vvp  -N ./generated/shinTest_clk.iverilog -lxt2 -fst|| true
+	./shinTest/check_testcase.py
+
+fstShin:
+	gtkwave ./generated/wave.fst 1>/dev/null 2>&1 &
+
+fstShinClk:
+	gtkwave ./generated/wave_clk.fst 1>/dev/null 2>&1 &
+
+clean:
+	rm -rf ./generated/log/* ./generated/shin/*.vh ./generated/shinTest.* ./generated/wave*.*