diff --git a/tb/shinTest/Makefile_vcs b/tb/shinTest/Makefile_vcs
new file mode 100644
index 0000000..70ff0e6
--- /dev/null
+++ b/tb/shinTest/Makefile_vcs
@@ -0,0 +1,53 @@
+.PHONY:com sim clean
+
+OUTPUT = shin_test
+
+VCS = vcs -sverilog +v2k -timescale=1ns/1ps                             \
+	-debug_all                                                    \
+	-full64                                                       \
+	-o ${OUTPUT}                                                  \
+	-l compile.log                                                \
+
+SIM = ./${OUTPUT} -l run.log
+
+testShin_vcs:
+	python3 ./shinTest/gen_pkt.py
+	${VCS} -f ./shinTest_vcs.f
+	${SIM}
+sim:
+	${SIM}
+
+testShin:
+	./shinTest/gen_pkt.py
+	mkdir -p generated/log
+	rm -rf generated/log/*
+	iverilog -Wall  \
+	-o ./generated/shinTest.iverilog  \
+	-y ./generated/shin \
+	-I ./generated/shin \
+	-D RANDOMIZE_REG_INIT \
+	./shinTest/ShinTopSpiTb.v
+	vvp  -N ./generated/shinTest.iverilog -lxt2  -fst || true
+	./shinTest/check_testcase.py
+
+testShinClk:
+	./shinTest/gen_pkt_clk.py
+	mkdir -p generated/log
+	rm -rf generated/log/*
+	iverilog -Wall  \
+	-o ./generated/shinTest_clk.iverilog  \
+	-y ./generated/shin \
+	-I ./generated/shin \
+	-D RANDOMIZE_REG_INIT \
+	./shinTest/ShinTopSpiTb_clk.v
+	vvp  -N ./generated/shinTest_clk.iverilog -lxt2 -fst|| true
+	./shinTest/check_testcase.py
+
+fstShin:
+	gtkwave ./generated/wave.fst 1>/dev/null 2>&1 &
+
+fstShinClk:
+	gtkwave ./generated/wave_clk.fst 1>/dev/null 2>&1 &
+
+clean:
+	rm -rf ./generated/log/* ./generated/shin/*.vh ./generated/shinTest.* ./generated/wave*.*
diff --git a/tb/shinTest/shinTest_vcs.f b/tb/shinTest/shinTest_vcs.f
new file mode 100644
index 0000000..4e016b9
--- /dev/null
+++ b/tb/shinTest/shinTest_vcs.f
@@ -0,0 +1,46 @@
++incdir+./generated/shin
+./shinTest/ShinTopSpiTb.v
+./generated/SimCDR/Queue.v
+./generated/SimCDR/b8b10Encode.v
+./generated/SimCDR/b8b10Decode.v
+./generated/SimCDR/CDROut.v
+./generated/SimCDR/CDRInMultiSample.v
+./generated/SimCDR/MPCDRIn.v
+./generated/SimCDR/SimCDR.v
+./generated/SimCDR/CDRInAxis.v
+./generated/back/do16p_top.v
+./generated/back/SpiSRAMUp.v
+./generated/back/di16_top.v
+./generated/back/MirrorSRAMDP.v
+./generated/back/spi_top.v
+./generated/back/BackBoardMst.v
+./generated/back/backBoardMstTop.v
+./generated/back/oser_rst.v
+./generated/back/do16c_top.v
+./generated/back/DOut16c.v
+./generated/back/SpiSRAMDown.v
+./generated/back/DOut16p.v
+./generated/back/defineParam.v
+./generated/back/DIn16.v
+./generated/back/SpiSlv.v
+./generated/shin/b4b5DualEncode.v
+./generated/shin/ShareSRAM2k.v
+./generated/shin/QSpiInterface.v
+./generated/shin/MasterParser.v
+./generated/shin/Queue.v
+./generated/shin/crc32_8.v
+./generated/shin/b8b10Encode.v
+./generated/shin/SMUnit_4.v
+./generated/shin/b4b5DualDecode.v
+./generated/shin/SMUnit.v
+./generated/shin/MstSlvSwitch.v
+./generated/shin/b8b10Decode.v
+./generated/shin/CDROut.v
+./generated/shin/SSpiInterface.v
+./generated/shin/SlaveParser.v
+./generated/shin/SlaveSendGen.v
+./generated/shin/SlaveRecParser.v
+./generated/shin/Interface.v
+./generated/shin/Queue_4.v
+./generated/shin/ShinTop.v
+./generated/shin/MPCDRIn.v
\ No newline at end of file