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删除CDR中的硬件CDR

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This commit is contained in:
Ruige Lee
2025-02-11 15:17:02 +08:00
parent 0dc8c40076
commit ecff635e83
2 changed files with 7 additions and 48 deletions
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23
src/main/scala/backBoard/ebus/CDROut.scala
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@@ -20,13 +20,9 @@ class CDROutIO extends Bundle{
class CDROut extends Module{
val io: CDROutIO = IO(new CDROutIO)
val crcUnit = Module(new crc32_8)
def STATE_IDLE = 0.U
def STATE_PREAMBLE = 1.U
def STATE_PAYLOAD = 2.U
def STATE_FCS = 3.U
val ETH_PRE = "h55".U(8.W)
val ETH_SFD = "hD5".U(8.W)
@@ -38,20 +34,12 @@ class CDROut extends Module{
val bitCnt = Reg(UInt(4.W))
val byteCnt = Reg(UInt(3.W)) //payload dont need to count
val crcOut = crcUnit.io.crc
val reset_crc = stateCurr === STATE_IDLE
crcUnit.reset := reset.asBool | reset_crc
crcUnit.io.dataIn := io.axis.bits.tdata
crcUnit.io.isEnable := io.axis.fire
val shiftData = RegInit(0.U(10.W))
stateNext := Mux1H(Seq(
(stateCurr === STATE_IDLE) -> ( Mux( io.axis.valid, STATE_PREAMBLE, STATE_IDLE )),
(stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === 7.U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_PREAMBLE )),
(stateCurr === STATE_PAYLOAD) -> ( Mux( io.axis.fire, Mux( io.axis.bits.tlast, STATE_FCS, STATE_PAYLOAD ), STATE_PAYLOAD ) ),
(stateCurr === STATE_FCS) -> ( Mux( (byteCnt === (3+1).U) & (bitCnt === 9.U), STATE_IDLE, STATE_FCS )),
(stateCurr === STATE_PAYLOAD) -> ( Mux( io.axis.fire & io.axis.bits.tlast, STATE_IDLE, STATE_PAYLOAD ) ),
))
io.serDat := shiftData.extract(9)
@@ -76,13 +64,6 @@ class CDROut extends Module{
))
} .elsewhen( stateCurr === STATE_PAYLOAD ){
shiftData := Dualb4b5Encoder(io.axis.bits.tdata)
} .elsewhen( stateCurr === STATE_FCS ){
shiftData := Mux1H(Seq(
( byteCnt === 0.U) -> Dualb4b5Encoder(~crcOut( 7,0) ),
( byteCnt === 1.U) -> Dualb4b5Encoder(~crcOut(15,8) ),
( byteCnt === 2.U) -> Dualb4b5Encoder(~crcOut(23,16)),
( byteCnt === 3.U) -> Dualb4b5Encoder(~crcOut(31,24)),
))
}
}
}
@@ -94,7 +75,7 @@ class CDROut extends Module{
when( bitCnt === 9.U ){
bitCnt := 0.U
} .otherwise{
bitCnt := bitCnt + 1.U
bitCnt := bitCnt + 1.U
}
}