From ecff635e83736139db5d33c451f65efd1c016e16 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Tue, 11 Feb 2025 15:17:02 +0800 Subject: [PATCH] =?UTF-8?q?=E5=88=A0=E9=99=A4CDR=E4=B8=AD=E7=9A=84?= =?UTF-8?q?=E7=A1=AC=E4=BB=B6CDR?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/ebus/CDRIn.scala | 32 ++++------------------ src/main/scala/backBoard/ebus/CDROut.scala | 23 ++-------------- 2 files changed, 7 insertions(+), 48 deletions(-) diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala index 5351509..2f8e577 100644 --- a/src/main/scala/backBoard/ebus/CDRIn.scala +++ b/src/main/scala/backBoard/ebus/CDRIn.scala @@ -93,18 +93,10 @@ trait CDRInAxis{ this: CDRInBase => val STATE_IDLE = 0.U val STATE_HEADER = 1.U val STATE_PAYLOAD = 2.U - val STATE_CRC = 3.U - - - val stateNext = Wire(UInt(2.W)) val stateCurr = RegNext( stateNext, STATE_IDLE ) - val crcUnit = Module(new crc32_8) - val crcOut = crcUnit.io.crc - val crcCmp = Reg(UInt(32.W)) - val bitCnt = Reg(UInt(4.W)) val byteCnt = RegInit(0.U(12.W)) @@ -124,8 +116,7 @@ trait CDRInAxis{ this: CDRInBase => Mux1H(Seq( (stateCurr === STATE_IDLE) -> ( Mux( checkSFD === Cat(Dualb4b5Encoder(ETH_PRE) , Dualb4b5Encoder(ETH_SFD)), STATE_HEADER, STATE_IDLE )), //IDLE (stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_HEADER ) ), - (stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen-1.U) ) & (bitCnt === 9.U), STATE_CRC, STATE_PAYLOAD )), // PAYLOAD - (stateCurr === STATE_CRC) -> ( Mux( (byteCnt === 3.U) & (bitCnt === 9.U), STATE_IDLE, STATE_CRC )), //CRC + (stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen-1.U) ) & (bitCnt === 9.U), STATE_IDLE, STATE_PAYLOAD )), // PAYLOAD )) @@ -151,9 +142,6 @@ trait CDRInAxis{ this: CDRInBase => } .elsewhen( stateCurr === STATE_PAYLOAD ){ byteCnt := Mux( byteCnt =/= (payloadLen-1.U), byteCnt + 1.U, 0.U ) assert( byteCnt <= ( payloadLen-1.U ) ) - } .elsewhen( stateCurr === STATE_CRC ){ - byteCnt := Mux( byteCnt =/= 3.U, byteCnt + 1.U, 0.U ) - assert( byteCnt <= 3.U ) } } @@ -162,9 +150,9 @@ trait CDRInAxis{ this: CDRInBase => val axis_valid = RegInit(false.B) - val axis_tdata = RegEnable( shiftData, bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) ) - val axis_tuser = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U & (crcOut =/= ~Cat( shiftData, crcCmp(31,8) )), bitCnt === 9.U ) - val axis_tlast = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U, bitCnt === 9.U ) + val axis_tdata = RegEnable( shiftData, bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) ) + val axis_tuser = false.B + val axis_tlast = RegNext( (byteCnt === (payloadLen-1.U) ) & (bitCnt === 9.U), false.B ) io.axis.valid := axis_valid io.axis.bits.tdata := axis_tdata @@ -174,20 +162,10 @@ trait CDRInAxis{ this: CDRInBase => when( io.axis.fire ){ axis_valid := false.B - } .elsewhen( bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) ){ + } .elsewhen( bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) ){ axis_valid := true.B } - when( stateCurr === STATE_CRC & bitCnt === 9.U ){ - crcCmp := Cat( shiftData, crcCmp(31,8) ) - } - - - crcUnit.io.isEnable := ((stateCurr === STATE_HEADER ) | (stateCurr === STATE_PAYLOAD )) & ( bitCnt === 9.U ) - crcUnit.io.dataIn := shiftData - - crcUnit.reset := reset.asBool | ( stateCurr === STATE_IDLE ) //idle - } diff --git a/src/main/scala/backBoard/ebus/CDROut.scala b/src/main/scala/backBoard/ebus/CDROut.scala index ec4d57c..f1df097 100644 --- a/src/main/scala/backBoard/ebus/CDROut.scala +++ b/src/main/scala/backBoard/ebus/CDROut.scala @@ -20,13 +20,9 @@ class CDROutIO extends Bundle{ class CDROut extends Module{ val io: CDROutIO = IO(new CDROutIO) - val crcUnit = Module(new crc32_8) - def STATE_IDLE = 0.U def STATE_PREAMBLE = 1.U def STATE_PAYLOAD = 2.U - def STATE_FCS = 3.U - val ETH_PRE = "h55".U(8.W) val ETH_SFD = "hD5".U(8.W) @@ -38,20 +34,12 @@ class CDROut extends Module{ val bitCnt = Reg(UInt(4.W)) val byteCnt = Reg(UInt(3.W)) //payload dont need to count - val crcOut = crcUnit.io.crc - val reset_crc = stateCurr === STATE_IDLE - crcUnit.reset := reset.asBool | reset_crc - - crcUnit.io.dataIn := io.axis.bits.tdata - crcUnit.io.isEnable := io.axis.fire - val shiftData = RegInit(0.U(10.W)) stateNext := Mux1H(Seq( (stateCurr === STATE_IDLE) -> ( Mux( io.axis.valid, STATE_PREAMBLE, STATE_IDLE )), (stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === 7.U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_PREAMBLE )), - (stateCurr === STATE_PAYLOAD) -> ( Mux( io.axis.fire, Mux( io.axis.bits.tlast, STATE_FCS, STATE_PAYLOAD ), STATE_PAYLOAD ) ), - (stateCurr === STATE_FCS) -> ( Mux( (byteCnt === (3+1).U) & (bitCnt === 9.U), STATE_IDLE, STATE_FCS )), + (stateCurr === STATE_PAYLOAD) -> ( Mux( io.axis.fire & io.axis.bits.tlast, STATE_IDLE, STATE_PAYLOAD ) ), )) io.serDat := shiftData.extract(9) @@ -76,13 +64,6 @@ class CDROut extends Module{ )) } .elsewhen( stateCurr === STATE_PAYLOAD ){ shiftData := Dualb4b5Encoder(io.axis.bits.tdata) - } .elsewhen( stateCurr === STATE_FCS ){ - shiftData := Mux1H(Seq( - ( byteCnt === 0.U) -> Dualb4b5Encoder(~crcOut( 7,0) ), - ( byteCnt === 1.U) -> Dualb4b5Encoder(~crcOut(15,8) ), - ( byteCnt === 2.U) -> Dualb4b5Encoder(~crcOut(23,16)), - ( byteCnt === 3.U) -> Dualb4b5Encoder(~crcOut(31,24)), - )) } } } @@ -94,7 +75,7 @@ class CDROut extends Module{ when( bitCnt === 9.U ){ bitCnt := 0.U } .otherwise{ - bitCnt := bitCnt + 1.U + bitCnt := bitCnt + 1.U } }