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tx/rx buff接口归一化

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This commit is contained in:
RuigeLee
2023-10-30 17:32:55 +08:00
parent beedc98977
commit eb8420e7f9
7 changed files with 99 additions and 216 deletions
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44
src/main/scala/Switch/DMA.scala
View File

@@ -8,7 +8,7 @@ import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import MAC._
abstract class DMAMstBase(val edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule{
@@ -27,8 +27,8 @@ abstract class DMAMstBase(val edgeOut: TLEdgeOut)(implicit p: Parameters) extend
val r_TxLen = Input(UInt(16.W))
val r_RxLen = Output(UInt(16.W))
val rxEnq = Vec(chn, Flipped(new Receive_Enq_Bundle))
val txDeq = Vec(chn, new Transmit_Bundle)
val rxEnq = Vec(chn, Flipped(Decoupled(new Mac_Stream_Bundle)))
val txDeq = Vec(chn, Decoupled(new Mac_Stream_Bundle))
}
@@ -59,9 +59,9 @@ trait DMAMstFSM{ this: DMAMstBase =>
stateNxt :=
Mux1H(Seq(
( stateCur === stateIdle ) -> Mux( (io.triTx & io.r_TxLen > 32.U), stateTx, Mux( rxBuff.io.deq.header.fire, stateRx, stateIdle ) ),
( stateCur === stateRx ) -> Mux( rxBuff.io.deq.ctrl.fire, stateIdle, stateRx ),
( stateCur === stateTx ) -> Mux( txBuff.io.enq.resp.fire, stateIdle, stateTx ),
( stateCur === stateIdle ) -> Mux( (io.triTx & io.r_TxLen > 32.U), stateTx, Mux( rxBuff.io.header.fire, stateRx, stateIdle ) ),
( stateCur === stateRx ) -> Mux( stateDMA === 0.U, stateIdle, stateRx ),
( stateCur === stateTx ) -> Mux( stateDMA === 0.U, stateIdle, stateTx ),
))
@@ -70,9 +70,9 @@ trait DMAMstFSM{ this: DMAMstBase =>
} .elsewhen( io.dmaMst.A.fire ){
stateDMA := 2.U
} .elsewhen( io.dmaMst.D.fire & isLastD ){
when( stateCur === stateTx & dmaAddress < (io.r_TxPtr + io.r_TxLen) ){
when( stateCur === stateTx & dmaAddress === (io.r_TxPtr + io.r_TxLen) ){
stateDMA := 0.U
} .elsewhen( stateCur === stateRx & rxBuff.io.deq.req.valid ){
} .elsewhen( stateCur === stateRx & ~rxBuff.io.deq.valid ){
stateDMA := 0.U
} .otherwise{
stateDMA := 1.U
@@ -96,10 +96,10 @@ trait DMAMstTileLink{ this: DMAMstBase =>
dmaAddress := dmaAddress + 1.U
}
rxBuff.io.deq.req.ready := io.dmaMst.A.fire & (stateCur === stateRx)
assert( ~(rxBuff.io.deq.req.ready & ~rxBuff.io.deq.req.valid) )
rxBuff.io.deq.ready := io.dmaMst.A.fire & (stateCur === stateRx)
assert( ~(rxBuff.io.deq.ready & ~rxBuff.io.deq.valid) )
rxBuff.io.deq.header.ready := ~(io.triTx & io.r_TxLen > 32.U) & stateCur === stateIdle
rxBuff.io.header.ready := ~(io.triTx & io.r_TxLen > 32.U) & stateCur === stateIdle
when( io.dmaMst.A.fire ){
dmaAValid := false.B
@@ -118,7 +118,7 @@ trait DMAMstTileLink{ this: DMAMstBase =>
fromSource = 0.U,
toAddress = dmaAddress,
lgSize = log2Ceil(8/8).U,
data = rxBuff.io.deq.req.bits.data,
data = rxBuff.io.deq.bits.data,
mask = "b1".U,
)._2
}
@@ -131,7 +131,7 @@ trait DMAMstTileLink{ this: DMAMstBase =>
io.dmaMst.D.ready :=
Mux1H(Seq(
( stateCur === stateRx ) -> true.B,
( stateCur === stateTx ) -> txBuff.io.enq.req.ready,
( stateCur === stateTx ) -> txBuff.io.enq.ready,
))
}
@@ -139,24 +139,22 @@ trait DMAMstBuff{ this: DMAMstBase =>
val rxLength = RegInit(0.U)
when( rxBuff.io.deq.req.fire ){
when( rxBuff.io.deq.req.bits.isStart ){
when( rxBuff.io.deq.fire ){
when( rxBuff.io.deq.bits.isStart ){
rxLength := 0.U
} .otherwise{
rxLength := rxLength + 1.U
}
}
io.triRx := rxBuff.io.deq.ctrl.fire
io.r_RxLen := RegEnable( rxLength, rxBuff.io.deq.ctrl.fire )
rxBuff.io.deq.ctrl.ready := stateCur === stateRx & io.dmaMst.D.fire & isLastD
io.triRx := rxBuff.io.deq.fire & rxBuff.io.deq.bits.isLast
io.r_RxLen := RegEnable( rxLength, io.triRx )
txBuff.io.enq.req.valid := io.dmaMst.D.valid & stateCur === stateTx
txBuff.io.enq.req.bits.data := io.dmaMst.D.bits.data
txBuff.io.enq.req.bits.isStart := dmaAddress === io.r_TxPtr
txBuff.io.enq.req.bits.isLast := dmaAddress === (io.r_TxPtr + io.r_TxLen)
txBuff.io.enq.resp.ready := true.B
txBuff.io.enq.valid := io.dmaMst.D.valid & stateCur === stateTx
txBuff.io.enq.bits.data := io.dmaMst.D.bits.data
txBuff.io.enq.bits.isStart := RegEnable( dmaAddress === io.r_TxPtr, io.dmaMst.A.fire)
txBuff.io.enq.bits.isLast := dmaAddress === (io.r_TxPtr + io.r_TxLen)
}

90
src/main/scala/Switch/RxBuff.scala
View File

@@ -5,31 +5,13 @@ import chisel3.util._
import MAC._
class Receive_Enq_Ctrl_Bundle extends Bundle{
// val LatchedRxLength = UInt(16.W)
val RxStatusInLatched = UInt(9.W)
}
class Receive_Deq_Ctrl_Bundle extends Receive_Enq_Ctrl_Bundle{
}
class Receive_Enq_Bundle extends Bundle{
val req = Decoupled(new Mac_Stream_Bundle)
val ctrl = Decoupled(new Receive_Enq_Ctrl_Bundle)
}
class Receive_Deq_Bundle extends Bundle{
val req = Decoupled(new Mac_Stream_Bundle)
val ctrl = Decoupled(new Receive_Deq_Ctrl_Bundle)
val header = Decoupled(Vec( 20, UInt(8.W) ) )
}
class RxBuffIO extends Bundle{
val enq = Flipped(new Receive_Enq_Bundle)
val deq = new Receive_Deq_Bundle
val enq = Flipped(Decoupled(new Mac_Stream_Bundle))
val deq = Decoupled(new Mac_Stream_Bundle)
val header = Decoupled(Vec( 20, UInt(8.W) ) )
}
@@ -46,18 +28,11 @@ class RxBuffBase extends Module{
val buff = for( i <- 0 until 2 ) yield { Module(new Queue( new Mac_Stream_Bundle, 2048 )) }
val info = for( i <- 0 until 2 ) yield { Reg(new Receive_Enq_Ctrl_Bundle) }
// dontTouch(buff(0).io.enq)
// dontTouch(info(0))
// dontTouch(buff(1).io.enq)
// dontTouch(info(1))
val header = for( i <- 0 until 2 ) yield { Reg(Vec( 20, UInt(8.W) )) }
val hValid = for( i <- 0 until 2 ) yield { RegInit(false.B) }
val cValid = for( i <- 0 until 2 ) yield { RegInit(false.B) }
val recCnt = RegInit(0.U(5.W))
@@ -68,35 +43,29 @@ trait RxBuffEnq{ this: RxBuffBase =>
buff(0).io.enq.valid := isEnqPi & io.enq.req.valid
buff(0).io.enq.bits := io.enq.req.bits
buff(0).io.enq.valid := isEnqPi & io.enq.valid
buff(0).io.enq.bits := io.enq.bits
buff(1).io.enq.valid := isEnqPo & io.enq.req.valid
buff(1).io.enq.bits := io.enq.req.bits
buff(1).io.enq.valid := isEnqPo & io.enq.valid
buff(1).io.enq.bits := io.enq.bits
io.enq.req.ready := (isEnqPi & buff(0).io.enq.ready) | (isEnqPo & buff(1).io.enq.ready)
io.enq.ctrl.ready := true.B
io.enq.ready := (isEnqPi & buff(0).io.enq.ready) | (isEnqPo & buff(1).io.enq.ready)
when( io.enq.ctrl.fire ){
when( io.enq.fire & io.enq.bits.isLast ){
isEnqPi := ~isEnqPi
when( isEnqPi ){
info(0) := io.enq.ctrl.bits
} .elsewhen( isEnqPo ){
info(1) := io.enq.ctrl.bits
}
}
when( io.enq.ctrl.fire ){
when( io.enq.fire ){
when( io.enq.bits.isStart ){
recCnt := 0.U
} .elsewhen( io.enq.req.fire ){
when( recCnt < 20.U ){
} .elsewhen( recCnt < 20.U ){
recCnt := recCnt + 1.U
when( isEnqPi ){
header(0)(recCnt) := io.enq.req.bits.data
header(0)(recCnt) := io.enq.bits.data
} .elsewhen( isEnqPo ){
header(1)(recCnt) := io.enq.req.bits.data
header(1)(recCnt) := io.enq.bits.data
} .otherwise{
assert(false.B, "Assert Failed, Rx Under Run")
}
@@ -109,44 +78,33 @@ trait RxBuffEnq{ this: RxBuffBase =>
trait RxBuffDeq{ this: RxBuffBase =>
when( io.deq.header.fire ){
when( io.header.fire ){
when( isDeqPi ) { hValid(0) := false.B }
when( isDeqPo ) { hValid(1) := false.B }
} .elsewhen( io.enq.req.fire & recCnt === 20.U ){
} .elsewhen( io.enq.fire & recCnt === 20.U ){
when( isEnqPi ) { hValid(0) := true.B }
when( isEnqPo ) { hValid(1) := true.B }
}
when( io.deq.ctrl.fire ){
when( io.deq.fire & io.deq.bits.isLast ){
isDeqPi := ~isDeqPi
when( isDeqPi ) { cValid(0) := false.B }
when( isDeqPo ) { cValid(1) := false.B }
} .elsewhen( io.enq.ctrl.fire ){
when( isEnqPi ) { cValid(0) := true.B }
when( isEnqPo ) { cValid(1) := true.B }
}
when( isDeqPi ){
io.deq.req <> buff(0).io.deq
io.deq <> buff(0).io.deq
buff(1).io.deq.ready := false.B
io.deq.header.valid := hValid(0)
io.deq.header.bits := header(0)
io.deq.ctrl.valid := cValid(0) & ~buff(0).io.deq.valid
io.deq.ctrl.bits := info(0)
io.header.valid := hValid(0)
io.header.bits := header(0)
} .otherwise{
assert( isDeqPo )
io.deq.req <> buff(1).io.deq
io.deq <> buff(1).io.deq
buff(0).io.deq.ready := false.B
io.deq.header.valid := hValid(1)
io.deq.header.bits := header(1)
io.deq.ctrl.valid := cValid(1) & ~buff(1).io.deq.valid
io.deq.ctrl.bits := info(1)
io.header.valid := hValid(1)
io.header.bits := header(1)
}

39
src/main/scala/Switch/TxBuff.scala
View File

@@ -7,28 +7,10 @@ import MAC._
// class Transmit_Req_Bundle extends Bundle{
// // val txLength = UInt(16.W)
// val PerPacketCrcEn = Bool()
// }
class Transmit_Resp_Bundle extends Bundle{
val RetryLimit = Bool()
val LateCollLatched = Bool()
val DeferLatched = Bool()
val CarrierSenseLost = Bool()
val isClear = Bool()
}
class Transmit_Bundle extends Bundle{
val req = Decoupled(new Mac_Stream_Bundle)
val resp = Flipped(Decoupled(new Transmit_Resp_Bundle))
}
class TxBuffIO extends Bundle{
val enq = Flipped(new Transmit_Bundle)
val deq = new Transmit_Bundle
val enq = Flipped(Decoupled(new Mac_Stream_Bundle))
val deq = Decoupled(new Mac_Stream_Bundle)
}
@@ -42,13 +24,13 @@ abstract class TxBuffBase extends Module{
trait TxBuffEnq{ this: TxBuffBase =>
io.enq.req <> buff.io.enq
io.enq <> buff.io.enq
when( io.enq.req.fire ){
when( io.enq.req.bits.isStart ) {
when( io.enq.fire ){
when( io.enq.bits.isStart ) {
enqCnt := 0.U
} .elsewhen( io.enq.req.bits.isLast ){
} .elsewhen( io.enq.bits.isLast ){
} .otherwise{
enqCnt := enqCnt + 1.U
@@ -59,12 +41,9 @@ trait TxBuffEnq{ this: TxBuffBase =>
trait TxBuffDeq{ this: TxBuffBase =>
io.deq.resp <> io.enq.resp
io.deq.req.bits := buff.io.deq.bits
io.deq.req.valid := buff.io.deq.valid
buff.io.deq.ready := io.deq.req.ready
io.deq.bits := buff.io.deq.bits
io.deq.valid := buff.io.deq.valid
buff.io.deq.ready := io.deq.ready
}

13
src/main/scala/Switch/mac/MAC.scala
View File

@@ -30,8 +30,8 @@ class MII extends Bundle with MDIO{
class MacIO extends Bundle{
val mii = new MII
val cfg = Flipped(new Mac_Config_Bundle)
val rxEnq = new Receive_Enq_Bundle
val txDeq = Flipped(new Transmit_Bundle)
val rxEnq = Decoupled(new Mac_Stream_Bundle)
val txDeq = Flipped(Decoupled(new Mac_Stream_Bundle))
// val int_o = Output(Bool())
@@ -568,16 +568,12 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
val req_ToAsync = Wire(new AsyncBundle(new Mac_Stream_Bundle))
val resp_ToAsync = Wire(new AsyncBundle(Bool()))
val fateRxRespPort = Wire( Flipped(Decoupled(Bool())) )
fateRxRespPort.ready := true.B
wishbone.io.rxReq <> FromAsyncBundle( req_ToAsync )
resp_ToAsync <> ToAsyncBundle( wishbone.io.rxResp )
withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset) {
req_ToAsync <> ToAsyncBundle( macTileLinkRx.io.rxReq )
fateRxRespPort <> FromAsyncBundle( resp_ToAsync )
}
@@ -612,9 +608,10 @@ val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( M
macTileLinkRx.io.LoadRxStatus := LoadRxStatus
macTileLinkRx.io.RxStatusIn := Cat(false.B, false.B, false.B, false.B, DribbleNibble, false.B, false.B, LatchedCrcError, RxLateCollision)
wishbone.io.rxEnq <> io.rxEnq
wishbone.io.txDeq <> io.txDeq
}

8
src/main/scala/Switch/mac/MacTileLinkRx.scala
View File

@@ -41,9 +41,15 @@ class MacTileLinkRx extends Module with RequireAsyncReset{
val ShiftWillEnd = RegInit(false.B)
// val LatchedRxLength = RegEnable(io.RxLength, 0.U(16.W), io.LoadRxStatus); io.LatchedRxLength := LatchedRxLength
val RxStatusInLatched = RegEnable(io.RxStatusIn, 0.U(9.W), io.LoadRxStatus); io.RxStatusInLatched := RxStatusInLatched
when( io.LoadRxStatus ) {
when( io.RxStatusIn.extract(4) ) { printf("Warning! DribbleNibble!\n"); }
when( io.RxStatusIn.extract(1) ) { printf("Warning! LatchedCrcError!\n"); }
when( io.RxStatusIn.extract(0) ) { printf("Warning! RxLateCollision!\n"); }
}
// val ShiftEnded_rck = RegInit(false.B); io.ShiftEnded_rck := ShiftEnded_rck
val RxEnableWindow = RegInit(false.B)

1
src/main/scala/Switch/mac/MacTileLinkTx.scala
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@@ -38,7 +38,6 @@ class MacTileLinkTx extends Module with RequireAsyncReset{
val TxStartFrm = RegInit(false.B); io.TxStartFrm := TxStartFrm
val TxEndFrm = RegInit(false.B); io.TxEndFrm := TxEndFrm
val TxData = RegInit(0.U(8.W)); io.TxData := TxData
// val LastWord = RegInit(false.B)
val ReadTxDataFromFifo_tck = RegInit(false.B);
// Generating delayed signals

116
src/main/scala/Switch/mac/MacTilelink.scala
View File

@@ -22,9 +22,7 @@ abstract class MacTileLinkBase() extends Module{
val r_RxEn = Input(Bool()) // Receive enable
val rxReq = Flipped(Decoupled(new Mac_Stream_Bundle))
val rxResp = Decoupled(new Bool())
// val LatchedRxLength_rxclk = Input(UInt(16.W))
val RxStatusInLatched_rxclk = Input(UInt(9.W))
val RxReady = Output(Bool())
@@ -32,7 +30,6 @@ abstract class MacTileLinkBase() extends Module{
val txReq = Decoupled(new Mac_Stream_Bundle)
// val TxEndFrm_wb = Output(Bool())
// Tx Status signals
@@ -51,8 +48,8 @@ abstract class MacTileLinkBase() extends Module{
val TxDoneSync = Input(Bool()) // Transmission ended
val rxEnq = new Receive_Enq_Bundle
val txDeq = Flipped(new Transmit_Bundle)
val rxEnq = Decoupled(new Mac_Stream_Bundle)
val txDeq = Flipped(Decoupled(new Mac_Stream_Bundle))
}
@@ -62,48 +59,28 @@ abstract class MacTileLinkBase() extends Module{
val ShiftEndedSyncPluse = io.rxReq.bits.isLast & io.rxReq.fire
val RxReady = RegInit(false.B); io.RxReady := RxReady
val rxBuffCtrlValid = RegInit(false.B)
io.rxEnq.ctrl.valid := rxBuffCtrlValid
// io.rxEnq.ctrl.bits.LatchedRxLength := RegEnable(io.LatchedRxLength_rxclk, ShiftEndedSyncPluse )
io.rxEnq.ctrl.bits.RxStatusInLatched := RegEnable(io.RxStatusInLatched_rxclk, ShiftEndedSyncPluse )
when( io.rxEnq.ctrl.fire ){
rxBuffCtrlValid := false.B
} .elsewhen( ShiftEndedSyncPluse ){
rxBuffCtrlValid := true.B
}
// RxReady generation
when(ShiftEndedSyncPluse ){
when(io.rxReq.bits.isLast & io.rxReq.fire ){
RxReady := false.B
} .elsewhen( io.r_RxEn & (io.rxEnq.req.ready) ){
} .elsewhen( io.r_RxEn & (io.rxEnq.ready) ){
RxReady := true.B
}
io.rxEnq.req.bits := io.rxReq.bits
io.rxEnq.req.valid := io.rxReq.valid
io.rxReq.ready := io.rxEnq.req.ready
io.rxEnq.bits := io.rxReq.bits
io.rxEnq.valid := io.rxReq.valid
io.rxReq.ready := io.rxEnq.ready
val rxRespValid = RegInit(false.B)
when( io.rxResp.fire ){
rxRespValid := false.B
} .elsewhen( ShiftEndedSyncPluse ){
rxRespValid := true.B
}
io.rxResp.valid := rxRespValid
io.rxResp.bits := DontCare
assert( ~(io.rxEnq.req.valid & ~io.rxEnq.req.ready), "Assert Failed, rx overrun!" )
assert( ~(io.rxEnq.valid & ~io.rxEnq.ready), "Assert Failed, rx overrun!" )
@@ -122,60 +99,30 @@ abstract class MacTileLinkBase() extends Module{
// val TxStartFrm_wb = RegInit(false.B)
// val TxEndFrm_wb = RegInit(false.B)
// val TxLength = RegInit(0.U(16.W))
val txDonePulse = io.TxDoneSync & ~RegNext(io.TxDoneSync, false.B)
val txAbortPulse = io.TxAbortSync & ~RegNext(io.TxAbortSync, false.B)
io.PerPacketCrcEn := false.B
// when( io.txDeq.req.fire ){
// TxStartFrm_wb := true.B
// } .elsewhen(io.txReq.fire){
// TxStartFrm_wb := false.B
// }
// when(((TxLength - 1.U) === 0.U) & io.TxUsedData){
// TxEndFrm_wb := true.B
// } .elsewhen(txDonePulse | txAbortPulse){
// TxEndFrm_wb := false.B
// }
// val TxLength = RegInit(0.U(16.W))
// when( io.txDeq.req.fire ){
// TxLength := io.txDeq.req.bits.txLength
// } .elsewhen( io.txDeq.data.fire ){
// when( TxLength < 1.U ){
// TxLength := 0.U
// } .otherwise{
// TxLength := TxLength - 1.U // Length is subtracted at the data request
// }
// }
when( txDonePulse | txAbortPulse ){
when(io.RetryLimit) {printf("Warning, io.RetryLimit\n")}
when(io.LateCollLatched) {printf("Warning, io.LateCollLatched\n")}
when(io.DeferLatched) {printf("Warning, io.DeferLatched\n")}
when(io.CarrierSenseLost) {printf("Warning, io.CarrierSenseLost\n")}
when(txAbortPulse) {printf("Warning, txAbortPulse\n")}
}
val txRespValid = RegInit(false.B)
val txRespBits = Reg(new Transmit_Resp_Bundle)
val killTrans = RegInit(false.B)
io.txDeq.resp.valid := txRespValid
io.txDeq.resp.bits := txRespBits
when( io.txDeq.resp.fire ){
txRespValid := false.B
} .elsewhen( txDonePulse | txAbortPulse ){
txRespValid := true.B
txRespBits.RetryLimit := io.RetryLimit
txRespBits.LateCollLatched := io.LateCollLatched
txRespBits.DeferLatched := io.DeferLatched
txRespBits.CarrierSenseLost := io.CarrierSenseLost
txRespBits.isClear := txAbortPulse
when( (io.txDeq.fire & io.txDeq.bits.isLast) | ~io.txDeq.valid ){
killTrans := false.B
} .elsewhen( txAbortPulse ){
killTrans := true.B
}
@@ -183,23 +130,22 @@ abstract class MacTileLinkBase() extends Module{
val isTxBusy = RegInit(false.B); io.txDeq.req.ready := ~isTxBusy & io.r_TxEn
val isTxEnable = RegInit(false.B)
when( io.txDeq.req.fire){
isTxBusy := true.B
} .elsewhen(txDonePulse | txAbortPulse){
isTxBusy := false.B
when( io.txDeq.fire & io.txDeq.bits.isLast & ~io.r_TxEn ){
isTxEnable := false.B
} .elsewhen( io.r_TxEn ){
isTxEnable := true.B
}
io.txDeq.ready := Mux( killTrans, true.B, isTxEnable & io.txReq.ready )
io.txReq.valid := Mux( killTrans, false.B, isTxEnable & io.txDeq.valid )
io.txReq.bits := io.txDeq.bits
// io.txReq.bits.isLast := TxEndFrm_wb
// io.txReq.bits.isStart := TxStartFrm_wb
// io.txReq.valid := io.txDeq.data.valid
// io.txDeq.data.ready := io.txReq.ready
io.txReq <> io.txDeq.req