92 lines
2.2 KiB
Scala
92 lines
2.2 KiB
Scala
package MAC
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import chisel3._
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import chisel3.util._
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class Mac_Stream_Bundle extends Bundle{
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val data = UInt(8.W)
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val isStart = Bool()
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val isLast = Bool()
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}
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class MacTileLinkRxIO extends Bundle{
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val rxReq = Decoupled(new Mac_Stream_Bundle)
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// val LatchedRxLength = Output(UInt(16.W))
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val RxStatusInLatched = Output( UInt(9.W) )
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// val RxLength = Input(UInt(16.W))
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val LoadRxStatus = Input(Bool())
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val RxStatusIn = Input(UInt(9.W))
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val Busy_IRQ_rck = Output(Bool())
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val Busy_IRQ_syncb = Input(Bool())
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val RxData = Input(UInt(8.W)) // Received data byte (from PHY)
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val RxValid = Input(Bool())
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val RxReady = Input(Bool())
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val RxStartFrm = Input(Bool())
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val RxEndFrm = Input(Bool())
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}
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class MacTileLinkRx extends Module with RequireAsyncReset{
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val io = IO(new MacTileLinkRxIO)
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val ShiftWillEnd = RegInit(false.B)
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val RxStatusInLatched = RegEnable(io.RxStatusIn, 0.U(9.W), io.LoadRxStatus); io.RxStatusInLatched := RxStatusInLatched
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when( io.LoadRxStatus ) {
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when( io.RxStatusIn.extract(4) ) { printf("Warning! DribbleNibble!\n"); }
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when( io.RxStatusIn.extract(1) ) { printf("Warning! LatchedCrcError!\n"); }
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when( io.RxStatusIn.extract(0) ) { printf("Warning! RxLateCollision!\n"); }
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}
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// val ShiftEnded_rck = RegInit(false.B); io.ShiftEnded_rck := ShiftEnded_rck
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val RxEnableWindow = RegInit(false.B)
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val Busy_IRQ_rck = RegInit(false.B); io.Busy_IRQ_rck := Busy_IRQ_rck
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// Indicating start of the reception process
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val SetWriteRxDataToFifo =
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io.RxValid & io.RxReady & (io.RxStartFrm | RxEnableWindow )
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// Generation of the end-of-frame signal
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when(io.RxStartFrm){
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RxEnableWindow := true.B
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} .elsewhen(io.RxEndFrm ){
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RxEnableWindow := false.B
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}
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when(io.RxValid & io.RxStartFrm & ~io.RxReady){
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Busy_IRQ_rck := true.B
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} .elsewhen(io.Busy_IRQ_syncb){
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Busy_IRQ_rck := false.B
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}
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val rxFifo = Module(new Queue(new Mac_Stream_Bundle, 4))
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rxFifo.io.enq.valid := SetWriteRxDataToFifo
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rxFifo.io.enq.bits.data := io.RxData
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rxFifo.io.enq.bits.isStart := io.RxStartFrm
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rxFifo.io.enq.bits.isLast := io.RxEndFrm
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assert( ~(rxFifo.io.enq.valid & ~rxFifo.io.enq.ready) )
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io.rxReq <> rxFifo.io.deq
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}
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