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tx/rx buff接口归一化

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This commit is contained in:
RuigeLee
2023-10-30 17:32:55 +08:00
parent beedc98977
commit eb8420e7f9
7 changed files with 99 additions and 216 deletions
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8
src/main/scala/Switch/mac/MacTileLinkRx.scala
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@@ -41,9 +41,15 @@ class MacTileLinkRx extends Module with RequireAsyncReset{
val ShiftWillEnd = RegInit(false.B)
// val LatchedRxLength = RegEnable(io.RxLength, 0.U(16.W), io.LoadRxStatus); io.LatchedRxLength := LatchedRxLength
val RxStatusInLatched = RegEnable(io.RxStatusIn, 0.U(9.W), io.LoadRxStatus); io.RxStatusInLatched := RxStatusInLatched
when( io.LoadRxStatus ) {
when( io.RxStatusIn.extract(4) ) { printf("Warning! DribbleNibble!\n"); }
when( io.RxStatusIn.extract(1) ) { printf("Warning! LatchedCrcError!\n"); }
when( io.RxStatusIn.extract(0) ) { printf("Warning! RxLateCollision!\n"); }
}
// val ShiftEnded_rck = RegInit(false.B); io.ShiftEnded_rck := ShiftEnded_rck
val RxEnableWindow = RegInit(false.B)