检回编译文件

This commit is contained in:
RuigeLee
2025-09-11 15:15:47 +08:00
parent 45a77fca12
commit ea7d91e9d3

23
src/test/scala/test.scala Normal file
View File

@@ -0,0 +1,23 @@
package test
import BACK._
import chisel3._
import chisel3.stage._
object testShinModule extends App {
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/shin/", "-e", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new ShinTop }),
))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/SimCDR/", "-e", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new SimCDR }),
))
}